ユーザーズマニュアル (80526PZ1000256)目次Introduction8Second Level (L2) Cache Implementation8Terminology91.1.1 Package and Processor Terminology91.1.2 Processor Naming Convention10Processor Identification10Related Documents11Electrical Specifications13Processor System Bus and VREF13Clock Control and Low Power States14AGTL+/AGTL Bus Topology in a Uniprocessor Configuration14AGTL+/AGTL Bus Topology in a Dual-Processor Configuration142.2.1 Normal State—State 1152.2.2 AutoHALT Powerdown State—State 215Stop Clock State Machine152.2.3 Stop-Grant State—State 3162.2.4 HALT/Grant Snoop State—State 4162.2.5 Sleep State—State 5162.2.6 Deep Sleep State—State 6172.2.7 Clock Control17Power and Ground Pins172.3.1 Phase Lock Loop (PLL) Power18Processor VccCMOS Package Routing18Decoupling Guidelines192.4.1 Processor VCCCORE and AGTL+ (AGTL) Decoupling19Processor System Bus Clock and Processor Clocking192.5.1 Mixing Processors of Different Frequencies20Voltage Identification20Differential Clocking Example20Voltage Identification Definition21Processor System Bus Unused Pins22Processor System Bus Signal Groups22System Bus Signal Groups 123System Bus Signal Groups (AGTL)1232.8.1 Asynchronous vs. Synchronous for System Bus Signals242.8.2 System Bus Frequency Select Signals (BSEL[1:0])25BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design25Maximum Ratings26Frequency Select Truth Table for BSEL[1:0]26Absolute Maximum Ratings26Processor DC Specifications27Voltage and Current Specifications282.10.1 ICC Slew Rate Specifications33Slew Rate (23A Load Step)33PL Slew Rate Data (23A)33AGTL / AGTL+ Signal Groups DC Specifications34Non-AGTL+ Signal Group DC Specifications34Non-AGTL Signal Group DC Specifications35AGTL / AGTL+ System Bus Specifications36Processor AGTL+ Bus Specifications36Processor AGTL Bus Specifications36System Bus AC Specifications372.12.1 I/O Buffer Model37System Bus AC Specifications (SET Clock)37System Bus Timing Specifications (Differential Clock)38System Bus AC Specifications (AGTL+ or AGTL Signal Group)39System Bus AC Specifications (CMOS Signal Group)40System Bus AC Specifications (Reset Conditions)40System Bus AC Specifications (APIC Clock and APIC I/O)40Platform Power-On Timings40Generic Clock Waveform41BCLK, PICCLK, and TCK Generic Clock Waveform42System Bus Valid Delay Timings42System Bus Setup and Hold Timings43System Bus Reset and Configuration Timings43Platform Power-On Sequence Timings44Power-On Reset and Configuration Timings45Signal Quality Specifications46Guidelines46Processor Pins46in a Differential Clock Platform for AGTL46AGTL+ / AGTL Signal Quality Specifications and Measurement Guidelines47BCLK, PICCLK Generic Clock Waveform at the Processor Pins47Pins47AGTL+ Signal Quality Specifications and Measurement Guidelines483.3.1 Overshoot/Undershoot Guidelines48Low to High AGTL+ Receiver Ringback Tolerance483.3.2 Overshoot/Undershoot Magnitude493.3.3 Overshoot/Undershoot Pulse Duration493.3.4 Activity Factor493.3.5 Reading Overshoot/Undershoot Specification Tables50Example Platform Information50Specifications51Processor Pins51133 MHz AGTL+/AGTL Signal Group Overshoot/Undershoot Tolerance52Processor Pins52Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform53Maximum Acceptable AGTL Overshoot/Undershoot Waveform53Guidelines543.4.1 Overshoot/Undershoot Guidelines54Ringback 1543.4.2 Ringback Specification553.4.3 Settling Limit Guideline55Processor Pins55the Processor Pins55Thermal Specifications and Design Considerations56Thermal Specifications56Processor Die Area57Design Power57Thermal Diode58Processor Functional Die Layout for FC-PGA58Processor Functional Die Layout for FC-PGA58Thermal Diode Parameters59Thermal Diode Interface59Mechanical Specifications60FC-PGA Mechanical Specifications60FC-PGA and FC-PGA2 Package Types60Package Dimensions61Intel® Pentium® III Processor Package Dimensions61Processor Die Loading Parameters for FC-PGA625.1.1 FC-PGA2 Mechanical Specifications63Package Dimensions for FC-PGA263Package Dimensions for Intel® Pentium® III Processor FC-PGA2 Package63FC-PGA2 Flatness Specification64Processor Case Loading Parameters for FC-PGA264Processor Markings655.2.1 Processor Markings for FC-PGA265Top Side Processor Markings for FC-PGA (up to CPUID 0x686H)65Top Side Processor Markings for FC-PGA (for CPUID 0x68AH))65Recommended Mechanical Keep-Out Zones66Top Side Processor Markings for FC-PGA266Volumetric Keep-Out for FC-PGA and FC-PGA266Processor Signal Listing67Component Keep-Out67Intel® Pentium® III Processor Pinout68Signal Listing in Order by Signal Name69Signal Listing in Order by Pin Number74Boxed Processor Specifications80Mechanical Specifications for the Boxed Intel® Pentium® III Processor806.1.1 Boxed Processor Thermal Cooling Solution Dimensions80Conceptual Boxed Intel® Pentium® III Processor for the PGA370 Socket80Dimensions of Mechanical Step Feature in Heatsink Base816.1.2 Boxed Processor Heatsink Weight826.1.3 Boxed Processor Thermal Cooling Solution Clip82Thermal Specifications826.2.1 Boxed Processor Cooling Requirements82Dimensions of Notches in Heatsink Base82Electrical Requirements for the Boxed Intel® Pentium® III Processor836.3.1 Fan Heatsink Power Supply83Heatsinks in the PGA370 Socket83Boxed Processor Fan Heatsink Power Cable Connector Description84Intel® Pentium® III Processor84Fan Heatsink Power and Signal Specifications84Processor Signal Description85Alphabetical Signals Reference85Signal Description85Signal Summaries92Output Signals92Input Signals92Input/Output Signals (Single Driver)94Input/Output Signals (Multiple Driver)94サイズ： 1010KBページ数： 94Language: Englishマニュアルを開く
