Intel Baby Furniture 210200-002 マニュアル

目次

• RES

  0
• What is the 8088?

  1
• 8088 Pipelined Architecture

  1
• Efficient Program Coding

  1
• iAPX 88 Megabyte Memory Addressing

  1
• The 8088's 16-Bit Instruction Set

  1
• Interfacing the 8088

  1
• Processor Extensions

  1
• Review

  1
• The iAPX 188 CPU

  1
• Benchmark Report: Intel® iAPX 88 vs. Zilog Z80

  1
• Microcomputer Block Diagram

  1
• 8088 CPU

  1
• Program Execution in Standard Microprocessor

  1
• Pipelined Internal Architecture

  1
• Parallel Operation in 8088 CPU

  1
• 8088 Register Set

  1
• Data Group Registers

  1
• Base and Index Registers

  1
• Control Registers

  1
• iAPX 88 Architecture Quick Access to Four Segment Types

  1
• How an Address is Built

  1
• Process Relocation

  1
• iAPX 88 Addressing Modes

  1
• Four-Component Addressing Example

  1
• Data Transfer Instructions

  1
• Arithmetic Instructions

  1
• Bit Manipulation Instructions

  1
• String Instructions

  1
• Program Transfer Instructions

  1
• Processor Control Instructions

  1
• 8088 Bus Interface is Similar to 8085

  1
• Multiplexed Bus Components for Low Chip-Count Applications

  1
• iAPX 88 Bipolar Support Components

  1
• iAPX 88 Longer Memory Access Time

  1
• iAPX 88 Processor Extensions

  1
• iAPX88

  1
• 1-,

  1
• iAPX 88 Architecture

  2
• Register Structure

  2
• Addressing Modes

  2
• Organization of Instruction Set

  2
• Assembly Language Programming

  2
• Instruction Set

  2
• How to Address One Million Bytes

  2
• 8088 Register Structure

  2
• Implicit Use of General Registers

  2
• Defining Bits in Instructions with One and Two Operands -:

  2
• Determing First Operand

  2
• Effective Addresses Used with Different Data Structures

  2
• 8088 Address Components

  2
• Reserved and Dedicated Memory Locations

  2
• Interrupt Vector Table in Memory

  2
• Effective Address Calculation Time

  2
• Translation Process

  2
• Assemblers and Compilers

  2
• Delimiters in ASM-86

  2
• 1 Architecture Features

  2
• CPU Pin Fu nctions

  3
• 8088 Bus Timing and Minimum Mode Status

  3
• Bus Interface

  3
• Memory and Peripheral Interface

  3
• Clock Generation

  3
• Reset

  3
• Ready Implementation and Timing

  3
• Interrupts

  3
• Bus Control Transfer

  3
• Maximum Mode Systems

  3
• 8088 CPU Pins

  3
• Time Multiplexing of Address and Data

  3
• Decoding of Status Signals S3-S6

  3
• iAPX 88 Multiplexed Bus System

  3
• iAPX 88 With Buffered Demultiplexed Busses

  3
• iAPX 88 Basic Machine Cycle

  3
• iAPX 88 Compatible Multiplexed Bus Components

  3
• Multiplexed Bus Connections

  3
• DemultiplexedBusConnections

  3
• iAPX 88 With Buffered Demultiplexed Busses

  3
• How 16-bit Data is Arranged in 8-bit Memory

  3
• Generating Clock Signal With 8284A

  3
• CPU State Following Reset

  3
• iAPX 88 Bus Condition During Reset

  3
• iAPX 88 Bus During Reset

  3
• 8284A Reset Circuit

  3
• Constant Current on Reset Circuit

  3
• Normally READY Wait State Timing

  3
• Normally Not READY Wait State Timing

  3
• Using ROY 1/RDY 2 to Generate READy

  3
• Using AEN1/AEN2 to Generate READY

  3
• Single Wait State Generator

  3
• Interrupt Acknowledge Sequence

  3
• Interrupt Vector Table in Memory

  3
• Interrupt Priorities

  3
• iAPX 88 Bus Condition During HOLD

  3
• iAPX 88 and 8237A Connections

  3
• HOLD/HLDA Timing

  3
• iAPX 88 Using Maximum Mode

  3
• Min.lMax. Mode Pin Assignments

  3
• Request Grant Sequence Time (Max. Mode Only)

  3
• iAPX 88/21 Configuration

  3
• Zilog Z80

  3
• Multiplexed System

  4
• iAPX 88 Demultiplexed System

  4
• iAPX 88-Based S100 Bus System

  4
• iAPX 88-Based CRT Controller

  4
• iAPX 88 Multiprocessing Systems

  4
• iAPX 88 Multiplexed System Design Example

  4
• iAPX 88 Demo Board Address Map

  4
• Vest Pocket Computer Component Layout

  4
• Vest Pocket Schematic

  4
• iAPX 88 Demultiplexed Bus System

  4
• 2114 Chip Select Connection

  4
• iAPX 88 S100 Bus System

  4
• iAPX 88 S100 Schematic

  4
• CRT Controller Block Diagram

  4
• 8276 Row Buffer Loading

  4
• Escape Character Recognition Code

  4
• iAPX 88 Multiprocessing System

  4
• Typical iAPX 88 Local Mode Configuration

  4
• Typical 8089 Remote Mode Configuration

  4
• iAPX 86,88 Multiprocessing System

  4
• 2 Execution Times iAPX 88 vs. Z80A

  5
• 3 Execution Times iAPX 88 vs. Z80B

  6
• 4 Execution Times with Comparable Memory Access

  6
• 5 Execution Times with Comparable Memory Access

  7
• 7 Memory Utilization (Bytes)

  8
• Table 7. Memory Utilization

  8
• Block Translate Flowchart

  14
• Bubble Sort'

  17
• Benchmark Report: Intel® iAPX 88 vs. Motorola MC6809

  20
• iAPX 88 VS. Motorola MC68D9

  20
• 1 Architecture Features

  21
• 2 Execution Times (5 MHz 88/10 vs. 2 MHz 6809)

  24
• RESULTS

  24
• 3 Execution Times with "Equal" Memory Access Times

  25
• Table 4. Memory Utilization

  25
• CONCLUSION

  27
• Block Move Flowchart

  31
• Character Search Flowchart

  34
• iAPX 88/10 16-Bit HMOS Microprocessor

  37
• 8284A Clock Generator and Driver for iAPX 88/10, iAPX 88/10 Processors

  64
• 8282/8283 Octal Latch

  72
• 8286/8287 Octal Bus Transceiver

  77