ユーザーズマニュアル目次Intel® IQ80332 I/O Processor1Introduction 191.1 Document Purpose and Scope91.2 Other Related Documents9Table 1. Intel® 80332 I/O Processor Related Documentation List91.3 Electronic Information10Table 2. Electronic Information101.4 Component References10Table 3. Component Reference101.5 Terms and Definitions11Table 4. Terms and Definitions111.6 Intel® 80332 I/O Processor12Figure 1. Intel® 80332 I/O Processor Block Diagram131.7 Intel® IQ80332 I/O Processor Evaluation Platform Board Features14Table 5. Summary of Features14Getting Started 2152.1 Kit Content152.2 Hardware Installation152.2.1 First-Time Installation and Test152.2.2 Power Requirements162.3 Factory Settings172.4 Development Strategy172.4.1 Supported Tool Buckets172.4.2 Contents of the Flash172.5 Target Monitors182.5.1 RedHat RedBoot182.6 Host Communications Examples192.6.1 Serial-UART Communication19Figure 2. Serial-UART Communication192.6.2 JTAG Debug Communication19Figure 3. JTAG Debug Communication192.6.3 Network Communication20Figure 4. Network Communication Example202.6.4 GNUPro GDB/Insight212.6.4.1 Communicating with RedBoot212.6.4.2 Connecting with GDB23Hardware Reference Section 3253.1 Functional Diagram25Figure 5. Functional Block Diagram253.2 Board Form-Factor/Connectivity26Table 6. Form-Factor/Connectivity Features26Figure 6. Board Form Factor263.3 Power27Table 7. Power Features273.4 Memory Subsystem283.4.1 DDR SDRAM283.4.1.1 Battery Backup283.4.2 Flash Memory Requirements29Table 8. Flash Memory Requirements293.5 Interrupt Routing30Table 9. External Interrupt Routing to Intel® 80332 I/O Processor303.6 Intel® IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus31Figure 7. Intel® IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus Topology31Table 10. Peripheral Bus Features313.6.1 Flash ROM32Table 11. Flash ROM Features32Figure 8. Flash Connection on Peripheral Bus323.6.2 UART333.6.3 Non-Volatile RAM333.6.4 Audio Buzzer333.6.5 HEX Display333.6.6 Rotary Switch33Table 12. Rotary Switch Requirements333.6.7 Battery Status34Table 13. Battery Status Buffer Requirements343.7 Debug Interface353.7.1 Console Serial Port353.7.2 JTAG Debug363.7.2.1 JTAG Port36Figure 9. JTAG Port Pin-out363.8 Board Reset Scheme37Table 14. Reset Requirements/Schemes37Figure 10. RESET Sources373.9 Switches and Jumpers383.9.1 Switch Summary38Table 15. Switch Summary383.9.2 Default Switch Settings of S7A1- Visual38Table 16. Switch S7A138Figure 11. Default Switch Setting Switch S7A1383.9.3 Jumper Summary39Table 17. Jumper Summary393.9.4 Connector Summary39Table 18. Connector Summary393.9.5 General Purpose Input/Output Header39Table 19. J2D2 GPIO Header Definition393.9.6 Detail Descriptions of Switches/Jumpers403.9.6.1 Switch S1C2: 80332 Reset403.9.6.2 Switch S6A1: BPCI-X Reset403.9.6.3 Switch S8A1: Rotary40Table 20. Rotary Switch Settings403.9.6.4 Switch S7A1403.9.6.4.1 S7A1-1: PCI-X Bus A Speed Enable corresponding to signal name PBI_AD340Table 21. S7A1-1: PCI-X Bus A Speed Enable403.9.6.4.2 S7A1-2: Reset IOP core corresponding to signal name PBI_AD540Table 22. Switch S7A1-2: Reset IOP: Settings and Operation Mode403.9.6.4.3 S7A1-3: Configration Cycle Enable corresponding to signal name PBI_AD641Table 23. Switch S7A1-3: RETRY: Settings and Operation Mode413.9.6.4.4 S7A1-4: PCI-X Bus B Speed Enable corresponding to signal name PBI_AD1041Table 24. S7A1-4: PCI-X Bus B Speed Enable: Settings and Operation Mode413.9.6.4.5 S7A1-5: PCI-X Bus B Hot-Plug Reset Disable corresponding to signal name PBI_AD1141Table 25. S7A1-5: PCI-X Bus B Hot-Plug Reset Disable: Settings and Operation Mode413.9.6.4.6 Switch S7A1- 6: Hot Plug Capable Disabled corresponding to signal name PBI_AD1541Table 26. Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode413.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 corresponding to signal name PBI_AD1742Table 27. Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode423.9.6.4.8 Switch S7A1 - 8: SMBUS Manageability Address Bit 3 corresponding to signal name PBI_AD1842Table 28. Switch S7A1 - 8: SMBUS Manageability Address Bit 3: Settings and Operation Mode423.9.6.4.9 Switch S7A1- 9:SMBUS Manageability Address Bit 2 corresponding to signal name PBI_AD1742Table 29. Switch S7A1 - 9: SMBUS Manageability Address Bit 2: Settings and Operation Mode423.9.6.4.10 Switch S7A1- 10: SMBUS Manageability Address Bit 1 corresponding to signal name PBI_AD1642Table 30. Switch S7A1 - 10: SMBUS Slave Address 0: Settings and Operation Mode423.9.6.5 Jumper J7D1: Flash bit-width43Table 31. Jumper J7D1: Descriptions43Table 32. Jumper J7D1: Settings and Operation Mode433.9.6.6 Jumper J1C1: JTAG Chain43Table 33. Jumper J1C1: Descriptions43Table 34. Jumper J1C1: Settings and Operation Mode433.9.6.7 Jumper J1D2: UART Control43Table 35. Jumper J1D2: Descriptions43Table 36. Jumper J1D2: Settings and Operation Mode433.9.6.8 Jumper J7B4: SMBus Header44Table 37. Jumper J7B4: Descriptions44Table 38. Jumper J7B4: Settings and Operation Mode443.9.6.9 Jumper J9D3: Buzzer Volume Control44Table 39. Jumper J9D3: Descriptions44Table 40. Jumper J9D3: Settings and Operation Mode44Software Reference 4454.1 DRAM454.2 Components on the Peripheral Bus454.2.1 Flash ROM46Figure 12. Flash Connection to Peripheral Bus464.2.2 Peripheral Bus Memory Map47Table 41. Peripheral Bus Memory Map474.3 Board Support Package (BSP) Examples484.3.1 Intel® 80332 I/O Processor Memory Map48Figure 13. Intel® 80332 I/O Processor Memory Map484.3.2 RedBoot* Intel® 80332 I/O Processor Memory Map494.3.3 RedBoot Intel® 80332 I/O Processor Files494.3.4 RedBoot 80332 DDR Memory Initialization Sequence50IQ80321 and IQ80332 Comparisons A51Table 42. Intel® IQ80321 Evaluation Platform Board and Intel® IQ80332 I/O processor evaluation platform board Comparisons51Getting Started and Debugger B53B.1 Introduction53B.1.1 Purpose53B.1.2 Necessary Hardware and Software53B.1.3 Related Documents53Table 43. Related Documents53B.1.4 Related Web Sites54B.2 Setup55B.2.1 Hardware Setup55Figure 14. Intel® 80332 I/O Processor Hardware Setup Flow Chart55B.2.2 Software Setup56Figure 15. Software Flow Diagram56B.3 New Project Setup57B.3.1 Creating a New Project57B.3.2 Configuration58B.4 Flashing with JTAG59B.4.1 Overview59B.4.2 Using Flash Programmer60B.5 Debugging Out of Flash61B.6 Building an Executable File From Example Code61B.7 Running the Code|Lab Debugger62B.7.1 Launching and Configuring Debugger62B.7.2 Manually Loading and Executing an Application Program62B.7.3 Displaying Source Code63B.7.4 Using Breakpoints63B.7.5 Stepping Through the Code64B.7.6 Setting Code|Lab Debug Options64B.8 Exploring the Code|Lab Debug Windows65B.8.1 Toolbar Icons65B.8.2 Workspace Window65B.8.3 Source Code65B.8.4 4 Debug and Console Windows65B.8.5 Memory Window65B.8.6 Registers Window66B.8.7 Watch Window66B.8.8 Variables Window66B.9 Debugging Basics67B.9.1 Overview67B.9.2 Hardware and Software Breakpoints67B.9.2.1 Software Breakpoints67B.9.2.2 Hardware Breakpoints67B.9.3 C.9.3 Exceptions/Trapping68サイズ： 610KBページ数： 68Language: Englishマニュアルを開く
ユーザーズマニュアル目次Intel® IQ80332 I/O Processor1Introduction 191.1 Document Purpose and Scope91.2 Other Related Documents9Table 1. Intel® 80332 I/O Processor Related Documentation List91.3 Electronic Information10Table 2. Electronic Information101.4 Component References10Table 3. Component Reference101.5 Terms and Definitions11Table 4. Terms and Definitions111.6 Intel® 80332 I/O Processor12Figure 1. Intel® 80332 I/O Processor Block Diagram131.7 Intel® IQ80332 I/O Processor Evaluation Platform Board Features14Table 5. Summary of Features14Getting Started 2152.1 Kit Content152.2 Hardware Installation152.2.1 First-Time Installation and Test152.2.2 Power Requirements162.3 Factory Settings172.4 Development Strategy172.4.1 Supported Tool Buckets172.4.2 Contents of the Flash172.5 Target Monitors182.5.1 RedHat RedBoot182.6 Host Communications Examples192.6.1 Serial-UART Communication19Figure 2. Serial-UART Communication192.6.2 JTAG Debug Communication19Figure 3. JTAG Debug Communication192.6.3 Network Communication20Figure 4. Network Communication Example202.6.4 GNUPro GDB/Insight212.6.4.1 Communicating with RedBoot212.6.4.2 Connecting with GDB23Hardware Reference Section 3253.1 Functional Diagram25Figure 5. Functional Block Diagram253.2 Board Form-Factor/Connectivity26Table 6. Form-Factor/Connectivity Features26Figure 6. Board Form Factor263.3 Power27Table 7. Power Features273.4 Memory Subsystem283.4.1 DDR SDRAM283.4.1.1 Battery Backup283.4.2 Flash Memory Requirements29Table 8. Flash Memory Requirements293.5 Interrupt Routing30Table 9. External Interrupt Routing to Intel® 80332 I/O Processor303.6 Intel® IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus31Figure 7. Intel® IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus Topology31Table 10. Peripheral Bus Features313.6.1 Flash ROM32Table 11. Flash ROM Features32Figure 8. Flash Connection on Peripheral Bus323.6.2 UART333.6.3 Non-Volatile RAM333.6.4 Audio Buzzer333.6.5 HEX Display333.6.6 Rotary Switch33Table 12. Rotary Switch Requirements333.6.7 Battery Status34Table 13. Battery Status Buffer Requirements343.7 Debug Interface353.7.1 Console Serial Port353.7.2 JTAG Debug363.7.2.1 JTAG Port36Figure 9. JTAG Port Pin-out363.8 Board Reset Scheme37Table 14. Reset Requirements/Schemes37Figure 10. RESET Sources373.9 Switches and Jumpers383.9.1 Switch Summary38Table 15. Switch Summary383.9.2 Default Switch Settings of S7A1- Visual38Table 16. Switch S7A138Figure 11. Default Switch Setting Switch S7A1383.9.3 Jumper Summary39Table 17. Jumper Summary393.9.4 Connector Summary39Table 18. Connector Summary393.9.5 General Purpose Input/Output Header39Table 19. J2D2 GPIO Header Definition393.9.6 Detail Descriptions of Switches/Jumpers403.9.6.1 Switch S1C2: 80332 Reset403.9.6.2 Switch S6A1: BPCI-X Reset403.9.6.3 Switch S8A1: Rotary40Table 20. Rotary Switch Settings403.9.6.4 Switch S7A1403.9.6.4.1 S7A1-1: PCI-X Bus A Speed Enable corresponding to signal name PBI_AD340Table 21. S7A1-1: PCI-X Bus A Speed Enable403.9.6.4.2 S7A1-2: Reset IOP core corresponding to signal name PBI_AD540Table 22. Switch S7A1-2: Reset IOP: Settings and Operation Mode403.9.6.4.3 S7A1-3: Configration Cycle Enable corresponding to signal name PBI_AD641Table 23. Switch S7A1-3: RETRY: Settings and Operation Mode413.9.6.4.4 S7A1-4: PCI-X Bus B Speed Enable corresponding to signal name PBI_AD1041Table 24. S7A1-4: PCI-X Bus B Speed Enable: Settings and Operation Mode413.9.6.4.5 S7A1-5: PCI-X Bus B Hot-Plug Reset Disable corresponding to signal name PBI_AD1141Table 25. S7A1-5: PCI-X Bus B Hot-Plug Reset Disable: Settings and Operation Mode413.9.6.4.6 Switch S7A1- 6: Hot Plug Capable Disabled corresponding to signal name PBI_AD1541Table 26. Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode413.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 corresponding to signal name PBI_AD1742Table 27. Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode423.9.6.4.8 Switch S7A1 - 8: SMBUS Manageability Address Bit 3 corresponding to signal name PBI_AD1842Table 28. Switch S7A1 - 8: SMBUS Manageability Address Bit 3: Settings and Operation Mode423.9.6.4.9 Switch S7A1- 9:SMBUS Manageability Address Bit 2 corresponding to signal name PBI_AD1742Table 29. Switch S7A1 - 9: SMBUS Manageability Address Bit 2: Settings and Operation Mode423.9.6.4.10 Switch S7A1- 10: SMBUS Manageability Address Bit 1 corresponding to signal name PBI_AD1642Table 30. Switch S7A1 - 10: SMBUS Slave Address 0: Settings and Operation Mode423.9.6.5 Jumper J7D1: Flash bit-width43Table 31. Jumper J7D1: Descriptions43Table 32. Jumper J7D1: Settings and Operation Mode433.9.6.6 Jumper J1C1: JTAG Chain43Table 33. Jumper J1C1: Descriptions43Table 34. Jumper J1C1: Settings and Operation Mode433.9.6.7 Jumper J1D2: UART Control43Table 35. Jumper J1D2: Descriptions43Table 36. Jumper J1D2: Settings and Operation Mode433.9.6.8 Jumper J7B4: SMBus Header44Table 37. Jumper J7B4: Descriptions44Table 38. Jumper J7B4: Settings and Operation Mode443.9.6.9 Jumper J9D3: Buzzer Volume Control44Table 39. Jumper J9D3: Descriptions44Table 40. Jumper J9D3: Settings and Operation Mode44Software Reference 4454.1 DRAM454.2 Components on the Peripheral Bus454.2.1 Flash ROM46Figure 12. Flash Connection to Peripheral Bus464.2.2 Peripheral Bus Memory Map47Table 41. Peripheral Bus Memory Map474.3 Board Support Package (BSP) Examples484.3.1 Intel® 80332 I/O Processor Memory Map48Figure 13. Intel® 80332 I/O Processor Memory Map484.3.2 RedBoot* Intel® 80332 I/O Processor Memory Map494.3.3 RedBoot Intel® 80332 I/O Processor Files494.3.4 RedBoot 80332 DDR Memory Initialization Sequence50IQ80321 and IQ80332 Comparisons A51Table 42. Intel® IQ80321 Evaluation Platform Board and Intel® IQ80332 I/O processor evaluation platform board Comparisons51Getting Started and Debugger B53B.1 Introduction53B.1.1 Purpose53B.1.2 Necessary Hardware and Software53B.1.3 Related Documents53Table 43. Related Documents53B.1.4 Related Web Sites54B.2 Setup55B.2.1 Hardware Setup55Figure 14. Intel® 80332 I/O Processor Hardware Setup Flow Chart55B.2.2 Software Setup56Figure 15. Software Flow Diagram56B.3 New Project Setup57B.3.1 Creating a New Project57B.3.2 Configuration58B.4 Flashing with JTAG59B.4.1 Overview59B.4.2 Using Flash Programmer60B.5 Debugging Out of Flash61B.6 Building an Executable File From Example Code61B.7 Running the Code|Lab Debugger62B.7.1 Launching and Configuring Debugger62B.7.2 Manually Loading and Executing an Application Program62B.7.3 Displaying Source Code63B.7.4 Using Breakpoints63B.7.5 Stepping Through the Code64B.7.6 Setting Code|Lab Debug Options64B.8 Exploring the Code|Lab Debug Windows65B.8.1 Toolbar Icons65B.8.2 Workspace Window65B.8.3 Source Code65B.8.4 4 Debug and Console Windows65B.8.5 Memory Window65B.8.6 Registers Window66B.8.7 Watch Window66B.8.8 Variables Window66B.9 Debugging Basics67B.9.1 Overview67B.9.2 Hardware and Software Breakpoints67B.9.2.1 Software Breakpoints67B.9.2.2 Hardware Breakpoints67B.9.3 C.9.3 Exceptions/Trapping68サイズ： 1.6MBページ数： 68Language: Englishマニュアルを開く
