ユーザーズマニュアル目次Contents3Figures5Tables6Revision History71.0 Introduction91.1 Content Overview91.2 Related Documentation101.3 Acronyms and Abbreviations111.4 Overview111.5 Typical Applications142.0 System Architecture152.1 System Architecture Description152.2 System Memory Map153.0 General Hardware Design Considerations173.1 Soft Fusible Features173.2 DDR-266 SDRAM Interface183.2.1 Signal Interface183.2.2 DDR SDRAM Memory Interface203.2.3 DDR SDRAM Initialization203.3 Expansion Bus203.3.1 Signal Interface213.3.2 Reset Configuration Straps213.3.3 8-Bit Device Interface233.3.4 16-Bit Device Interface233.3.5 32-Bit Device Interface243.3.6 Flash Interface273.3.7 SRAM Interface283.3.8 Design Notes283.4 UART Interface283.4.1 Signal Interface293.5 MII/SMII Interface303.5.1 Signal Interface MII313.5.2 Device Connection, MII333.5.3 Signal Interface, SMII343.5.4 Device Connection, SMII353.6 GPIO Interface353.6.1 Signal Interface363.6.2 Design Notes363.7 I2C Interface373.7.1 Signal Interface373.7.2 Device Connection373.8 USB Interface383.8.1 Signal Interface393.8.2 Device Connection403.9 UTOPIA Level 2 Interface413.9.1 Signal Interface423.9.2 Device Connection423.10 HSS Interface433.10.1 Signal Interface443.10.2 Device Connection463.11 SSP Interface463.11.1 Signal Interface473.11.2 Device Connection473.12 PCI Interface483.12.1 Signal Interface483.12.2 PCI Interface Block Diagram493.12.3 Supporting 5 V PCI Interface503.12.4 PCI Option Interface513.12.5 Design Notes533.13 JTAG Interface533.13.1 Signal Interface543.14 Input System Clock543.14.1 Clock Signals543.14.2 Clock Oscillator543.14.3 Device Connection553.15 Power553.15.1 De-Coupling Capacitance Recommendations563.15.2 VCC De-Coupling563.15.3 VCCP De-Coupling563.15.4 VCCM De-Coupling563.15.5 Power Sequence563.15.6 Reset Timing564.0 General PCB Guide594.1 PCB Overview594.2 General Recommendations594.3 Component Selection594.4 Component Placement594.5 Stack-Up Selection605.0 General Layout and Routing Guide635.1 Overview635.2 General Layout Guidelines635.2.1 General Component Spacing645.2.2 Clock Signal Considerations665.2.3 SMII Signal Considerations675.2.4 MII Signal Considerations675.2.5 USB Considerations675.2.6 Cross-Talk685.2.7 EMI-Design Considerations685.2.8 Trace Impedance695.2.9 Power and Ground Plane696.0 PCI Interface Design Considerations716.1 Electrical Interface716.2 Topology716.3 Clock Distribution726.3.1 Trace Length Limits736.3.2 Routing Guidelines746.3.3 Signal Loading747.0 DDR-SDRAM757.1 Introduction757.1.1 Selecting VTT Power Supply807.1.2 Signal-Timing Analysis817.1.3 Printed Circuit Board Layer Stackup847.1.4 Printed Circuit Board Controlled Impedance857.1.5 Timing Relationships877.1.6 Resistive Compensation Register (Rcomp)887.1.7 Routing Guidelines887.1.7.1 Clock Group887.1.7.2 Data, Command, and Control Groups897.2 Simulation Results907.2.1 Clock Group907.2.2 Data Group927.2.3 Control Group987.2.4 Command Group1007.2.5 RCVENIN and RCVENOUT105サイズ: 1.67MBページ数: 108Language: Englishマニュアルを開く