Intel LV 1.10 GHz マニュアル

目次

• 1 Introduction

  7
  • 1.1 Terminology

    8
  • 1.2 References

    9
• 2 Low Power Features

  11
  • 2.1 Clock Control and Low Power States

    11
    • 2.1.1 Normal State

      11
    • 2.1.2 AutoHALT Powerdown State

      11
    • 2.1.3 HALT/Grant Snoop State

      12
    • 2.1.4 Sleep State

      12
    • 2.1.5 Deep Sleep State

      13
    • 2.1.6 Deeper Sleep State

      13
  • 2.2 Enhanced Intel SpeedStep® Technology

    13
  • 2.3 Processor System Bus Low Power Enhancements

    14
  • 2.4 Processor Power Status Indicator (PSI#) Signal

    15
• 3 Electrical Specifications

  17
  • 3.1 System Bus and GTLREF

    17
  • 3.2 Power and Ground Pins

    17
  • 3.3 Decoupling Guidelines

    17
    • 3.3.1 VCC Decoupling

      18
    • 3.3.2 System Bus AGTL+ Decoupling

      18
    • 3.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking

      18
  • 3.4 Voltage Identification

    18
  • 3.5 Catastrophic Thermal Protection

    20
  • 3.6 Signal Terminations and Unused Pins

    20
  • 3.7 System Bus Signal Groups

    20
  • 3.8 CMOS Signals

    21
  • 3.9 Maximum Ratings

    22
  • 3.10 Processor DC Specifications

    22
• 4 Package Mechanical Specifications and Pin Information

  39
  • 4.1 Processor Pin-Out and Pin List

    47
  • 4.2 Alphabetical Signals Reference

    62
• 5 Thermal Specifications and Design Considerations

  69
  • 5.1 Thermal Specifications

    71
    • 5.1.1 Thermal Diode

      71
    • 5.1.2 Intel Thermal Monitor

      72
• 6 Debug Tools Specifications

  75
  • 6.1 Logic Analyzer Interface (LAI)

    75
    • 6.1.1 Mechanical Considerations

      75
    • 6.1.2 Electrical Considerations

      75