Intel MultiProcessor マニュアル

目次

• MultiProcessor Specification

  1
• Disclaimer

  2
• Revision Histoy

  3
• Table of Contents

  5
• 1 Introduction

  11
  • 1.1 Goals

    11
  • 1.2 Features of the Specification

    12
  • 1.3 Scope

    12
  • 1.4 Target Audience

    13
  • 1.5 Organization of This Document

    13
  • 1.6 Conventions Used in This Document

    14
  • 1.7 For More Information

    14
• 2 System Overview

  15
  • 2.1 Hardware Overview

    16
    • 2.1.1 System Processors

      16
    • 2.1.2 Advanced Programmable Interrupt Controller

      17
    • 2.1.3 System Memory

      18
    • 2.1.4 I/O Expansion Bus

      18
  • 2.2 BIOS Overview

    19
  • 2.3 Operating System Overview

    19
• 3 Hardware Specification

  21
  • 3.1 System Memory Configuration

    21
  • 3.2 System Memory Cacheability and Shareability

    22
  • 3.3 External Cache Subsystem

    24
  • 3.4 Locking

    24
  • 3.5 Posted Memory Write

    25
  • 3.6 Multiprocessor Interrupt Control

    25
    • 3.6.1 APIC Architecture

      25
    • 3.6.2 Interrupt Modes

      26
      • 3.6.2.1 PIC Mode

        27
      • 3.6.2.2 Virtual Wire Mode

        29
      • 3.6.2.3 Symmetric I/O Mode

        31
    • 3.6.3 Assignment of System Interrupts to the APIC Local Unit

      32
    • 3.6.4 Floating Point Exception Interrupt

      32
    • 3.6.5 APIC Memory Mapping

      32
    • 3.6.6 APIC Identification

      33
    • 3.6.7 APIC Interval Timers

      33
    • 3.6.8 Multiple I/O APIC Configurations

      33
  • 3.7 RESET Support

    34
    • 3.7.1 System-wide RESET

      34
    • 3.7.2 System-wide INIT

      35
    • 3.7.3 Processor-specific INIT

      35
  • 3.8 System Initial State

    36
  • 3.9 Support for Fault-resilient Booting

    36
• 4 MP Configuration Table

  37
  • 4.1 MP Floating Pointer Structure

    39
  • 4.2 MP Configuration Table Header

    41
  • 4.3 Base MP Configuration Table Entries

    42
    • 4.3.1 Processor Entries

      43
    • 4.3.2 Bus Entries

      46
    • 4.3.3 I/O APIC Entries

      48
    • 4.3.4 I/O Interrupt Assignment Entries

      48
    • 4.3.5 Local Interrupt Assignment Entries

      51
  • 4.4 Extended MP Configuration Table Entries

    53
    • 4.4.1 System Address Space Mapping Entries

      54
    • 4.4.2 Bus Hierarchy Descriptor Entry

      57
    • 4.4.3 Compatibility Bus Address Space Modifier Entry

      58
• 5 Default Configurations

  61
  • 5.1 Discrete APIC Configurations

    62
  • 5.2 Integrated APIC Configurations

    64
  • 5.3 Assignment of I/O Interrupts to the APIC I/O Unit

    66
    • 5.3.1 EISA and IRQ13

      67
    • 5.3.2 Level-triggered Interrupt Support

      67
  • 5.4 Assignment of System Interrupts to the APIC Local Unit

    67
• A System BIOS Programming Guidelines

  69
  • A.1 BIOS Post Initialization

    69
  • A.2 Controlling the Application Processors

    70
  • A.3 Programming the APIC for Virtual Wire Mode

    70
  • A.4 Constructing the MP Configuration Table

    72
• B Operating System Programming Guidelines

  75
  • B.1 Operating System Boot-up

    75
  • B.2 Operating System Booting and Self-configuration

    76
  • B.3 Interrupt Mode Initialization and Handling

    76
  • B.4 Application Processor Startup

    77
    • B.4.1 USING INIT IPI

      78
    • B.4.2 USING STARTUP IPI

      79
  • B.5 AP Shutdown Handling

    79
  • B.6 Other IPI Applications

    80
    • B.6.1 Handling Cache Flush

      80
    • B.6.2 Handling TLB Invalidation

      80
    • B.6.3 Handling PTE Invalidation

      80
  • B.7 Spurious APIC Interrupts

    80
  • B.8 Supporting Unequal Processors

    81
• C System Compliance Checklist

  83
• D Multiple I/O APIC Multiple PCI Bus Systems

  85
  • D.1 Interrupt Routing with Multiple APICs

    85
    • D.1.1 Variable Interrupt Routing

      85
    • D.1.2 Fixed Interrupt Routing

      86
  • D.2 Bus Entries in Systems with More Than One PCI Bus

    87
  • D.3 I/O Interrupt Assignment Entries for PCI Devices

    87
• E Errata

  89
• Glossary

  95