Intel S2600JFF マニュアル

ユーザーズマニュアル (BBS2600JFF)

1. Introduction
1
Section Outline
1
Server Board Use Disclaimer
2
2. Server Board Overview
3
Figure 1. Intel® Server Board S2600JF (InfiniBand* SKU)
3
Table 1. Intel® Server Board S2600JF Feature Set
3
Server Board Connector and Component Layout
5
Figure 2. Intel® Server Board S2600JF components
5
2.1.1 Board Rear Connector Placement
6
Figure 3. Rear Panel Connector Placement
6
2.1.2 Server Board Mechanical Drawings
7
Figure 4. Baseboard and Mounting holes
7
3. Product Architecture Overview
8
High Level Product Features
8
Table 2. Intel® Server Board S2600JF Features
8
Figure 5. Intel® Server Board S2600JF Functional Block Diagram
9
Processor Support
10
3.2.1 Processor Socket Assembly
10
Figure 6. Processor Socket Assembly
10
3.2.2 Processor Population Rules
11
Figure 7. Processor Socket ILM Variations
11
Table 3. Mixed Processor Configurations
12
Processor Function Overview
13
3.3.1 Intel® QuickPath Interconnect
14
3.3.2 Integrated Memory Controller (IMC) and Memory Subsystem
14
Figure 8. Processor with IMC Functional Block Diagram
14
Table 4. UDIMM Support Guidelines
16
Table 5. RDIMM Support Guidelines
16
Table 6. LRDIMM Support Guidelines
16
Figure 9. Intel® Server Board S2600JF family DIMM Slot Layout
17
Table 7. Intel® Server Board S2600JF DIMM Nomenclature
17
3.3.3 Processor Intergrated I/O Module (I/O)
19
Figure 10. General Functional Block Diagram of Processor I/O Sub-system
20
Figure 11.PCI Express* Lane distribution scheme
21
Figure 12. PCIe Riser for Slot 1
22
Table 8. CPU1 and CPU2 PCIe Connectivity
22
Intel® C600-A/B PCH Functional Overview
23
Figure 13. PCIe Riser for Slot 2
23
3.4.1 PCI Express*
24
Figure 14. Intel® C600-A/B PCH connection
24
3.4.2 Non-Transparent Bridge
25
3.4.3 Universal Serial Bus (USB)
25
3.4.4 Serial Attached SCSI (SAS) and Serial ATA (SATA) Controller
25
Table 9. Intel® Server Board S2600JF SATA/SAS port
26
Table 10. Intel® RAID C600 Storage Upgrade Key Options for S2600JF
26
3.4.5 PCI Interface
27
3.4.6 Low Pin Count (LPC) Interface
27
3.4.7 Digital Media Interface (DMI)
27
3.4.8 Serials Peripheral Interface (SPI)
27
3.4.9 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
27
3.4.10 Advanced Programmable Interrupt Controller (APIC)
28
3.4.11 Real Time Clock (RTC)
28
3.4.12 GPIO
28
3.4.13 Enhanced Power Management
28
3.4.14 Fan Speed Control
28
3.4.15 Intel® Virtualization Technology for Direct I/O (Intel® VT-d)
28
3.4.16 KVM/Serial Over LAN (SOL) Function
29
3.4.17 IDE-R Function
29
3.4.18 Manageability
29
3.4.19 System Management Bus (SMBus 2.0*)
30
3.4.20 Network Interface Controller (NIC)
30
Figure 15. 1GbE NIC port LED
31
Table 11. NIC Status LED
31
InfiniBand* Controller
32
3.5.1 Device Interfaces
32
Figure 16. ConnectX®-3 function block diagram
32
3.5.2 Quad Small Form-factor Pluggable (QSFP) connector
33
Figure 17. Connection between ConnectX®-3 and QSFP
33
Table 12. Network port configuration
33
Integrated Baseboard Management Controller Overview
34
Figure 18. Integrated BMC implementation overview
34
Figure 19. Integrated BMC Functional Block Diagram
34
3.6.1 Super I/O Controller
35
3.6.2 Graphics Controller and Video Support
36
Table 13. Supported Video Modes
36
3.6.3 Remote KVM
37
Table 14. Dual Video Option
37
4. Platform Management Functional Overview
38
Baseboard Management Controller (BMC) Firmware Feature Support
38
4.1.1 IPMI 2.0 Features
38
4.1.2 Non IPMI Features
39
4.1.3 New Manageability Features
40
Advanced Configuration and Power Interface (ACPI)
42
Platform Management SMBus* and I2C Implementation
42
Table 15. ACPI Power States
42
BMC Internal Timestamp Clock
43
Sensor Monitoring
43
Messaging Interfaces
43
4.6.1 Channel Management
43
4.6.2 User Model
44
Table 16. Standard Channel Assignments
44
Table 17. Default User Values
44
4.6.3 Sessions
45
Table 18. Channel/Media-specific minimum number of sessions
45
4.6.4 BMC LAN Channels
46
4.6.5 IPV6 Support
47
System Event Log (SEL)
48
4.7.1 Servicing Events
49
4.7.2 SEL Entry Deletion
49
4.7.3 SEL Erasure
49
4.7.4 SEL Extension Capabilities
49
Sensor Data Record (SDR) Repository
49
Field Replaceable Unit (FRU) Inventory Device
50
Diagnostics and Beep Code Generation
50
Diagnostics Interrupt (NMI)
50
Table 19. BMC Beep Codes
50
BMC Basic and Advanced Management Features
51
Table 20. NMI Signal Generation and Event Logging
51
Table 21. Basic and Advanced Management Features
51
4.12.1 Enabling Advanced Manageability Features
52
Table 22. Management features and Benefits
52
4.12.2 Media Redirection
54
4.12.3 Embedded Web server
55
4.12.4 Data Center Management Interface (DCMI)
56
4.12.5 Local Directory Authentication Protocol (LDAP)
57
4.12.6 Platform/Chassis Management
57
4.12.7 Thermal Control
57
Table 23. Fan Profile Mapping
58
4.12.8 Node Power On/Off Control
59
Intel® Intelligent Power Node Manager
59
4.13.1 Overview
59
4.13.2 Features
59
Management Engine (ME)
60
4.14.1 Overview
60
4.14.2 BMC – Management Engine (ME) Distributed Model
60
4.14.3 ME System Management Bus (SMBus*) Interface
61
4.14.4 BMC - Management Engine Interaction
61
Figure 20. Management Engine Distribution Model
61
4.14.5 ME Power and Firmware Startup
62
4.14.6 SmaRT/CLST
62
Other Platform Management
63
4.15.1 Wake On LAN (WOL)
63
4.15.2 PCI Express* Power management
63
4.15.3 PMBus*
63
4.15.4 Node Power Policies
63
5. BIOS Setup Interface
64
HotKeys Supported During POST
64
POST Logo/Diagnostic Screen
64
Table 24. POST HotKeys Recognized
64
BIOS Boot Pop-up Menu
65
BIOS Setup Utility
65
5.4.1 BIOS Setup Operation
65
Table 25. BIOS Setup Page Layout
66
Table 26. BIOS Setup: Keyboard Command Bar
67
5.4.2 BIOS Setup Utility Screens
68
Table 27. Screen Map
70
Figure 21. Main Screen
71
Table 28. Setup Utility – Main Screen Fields
71
Figure 22. Advanced Screen
73
Table 29. Setup Utility – Advanced Screen Display Fields
73
Figure 23. Processor Configuration Screen
74
Table 30. Setup Utility – Processor Configuration Screen Fields
74
Figure 24. Power and Performance Configuration Screen
78
Table 31. Setup Utility – Power and Performance Configuration Screen Fields
78
Table 32. Power/Performance Profiles
78
Figure 25. Memory Configuration Screen
80
Table 33. Setup Utility – Memory Configuration Screen Fields
81
Figure 26. Memory RAS and Performance Configuration Screen
82
Table 34. Setup Utility – Memory RAS and Performance Configuration Fields
82
Figure 27. Mass Storage Controller Configuration Screen
84
Table 35. Setup Utilities – Mass Storage Controller Configuration Fields
84
Figure 28. PCI Configuration Screen
85
Table 36. Setup Utility – PCI Configuration Screen Fields
86
Figure 29. NIC Configuration Screen
88
Table 37. Setup Utility – NIC Configuration Screen Fields
88
Figure 30. Serial Port Configuration Screen
91
Table 38. Setup Utility – Serial Ports Configuration Screen Fields
91
Figure 31. USB Configuration Screen
92
Table 39. Setup Utility – USB Controller Configuration Screen Fields
92
Figure 32. System Acoustic and Performance Configuration
93
Table 40. Setup Utility – System Acoustic and Performance Configuration Screen Fields
94
Figure 33. Security Screen
96
Table 41. Setup Utility – Security Configuration Screen Fields
96
Figure 34. Server Management Screen
98
Table 42. Setup Utility – Server Management Configuration Screen Fields
98
Figure 35. Console Redirection Screen
100
Table 43. Setup Utility – Console Redirection Configuration Fields
100
Figure 36. System Information Screen
102
Table 44. Setup Utility – Server Management System Information Fields
102
Figure 37. BMC LAN Configuration Screen
104
Table 45. Setup Utility — BMC configuration Screen Fields
104
Figure 38. Boot Options Screen
106
Table 46. Setup Utility – Boot Options Screen Fields
107
Figure 39. Hard Disk Order Screen
108
Table 47. Setup Utility – Hard Disk Order Fields
108
Figure 40. Network Device Order Screen
109
Figure 41. Delete EFI Boot Option Screen
109
Table 48. Setup Utility – Network Device Order Fields
109
Table 49. Setup Utility – Delete Boot Option Fields
109
Figure 42. Boot Manager Screen
110
Table 50. Setup Utility – Boot Manager Screen Fields
110
Figure 43. Error Manager Screen
111
Figure 44. Exit Screen
111
Table 51. Setup Utility – Error Manager Screen Fields
111
Loading BIOS Defaults
112
Table 52. Setup Utility – Exit Screen Fields
112
6. Configuration Jumpers
113
Figure 45. Jumper Blocks (J6B1, J1E2, J1E3, J1E1, J1D5)
113
6.1.1 Force Integrated BMC Update (J6B1)
114
Table 53. Server Board Jumpers (J6B1, J1E2, J1E3, J1E1, J1D5)
114
Table 54. Force Integrated BMC Update Jumper
114
6.1.2 Force ME Update (J1E2)
115
6.1.3 Password Clear (J1E3)
115
Table 55. Force ME Update Jumper
115
6.1.4 BIOS Recovery Mode (J1E1)
116
Table 56. Password Clear Jumper
116
Table 57. BIOS Recovery Mode Jumper
116
6.1.5 Reset BIOS Settings (J1D5)
117
Table 58. Reset BIOS Jumper
117
7. Connector/Header Locations and Pin-out
119
Power Connectors
119
System Management Headers
119
7.2.1 Intel® Remote Management Module 4 (Intel® RMM4 Lite) Connector
119
7.2.2 IPMB Header
119
Bridge Board Connector
119
Table 59. Main Power Supply Connector 6-pin 2x3 Connector (J4K1 and J3K1)
119
Table 60. Intel® RMM4 Lite Connector Pin-out (J1A2)
119
Table 61. IPMB Header 4-pin (J2D2)
119
Table 62. Bridge Board Connector (J1D1)
120
7.3.1 Power Button
121
7.3.2 Reset Button
121
7.3.3 Chassis Identify Button
121
7.3.4 Power LED
121
Table 63. Power LED Indicator States
121
7.3.5 System Status LED
122
Figure 46. System Status LED (A) and ID LED (B)
122
Table 64. System Status LED
122
7.3.6 Chassis ID LED
124
I/O Connectors
124
7.4.1 PCI Express* Connectors
124
Table 65. Chassis ID LED Indicator States
124
Table 66. PCI Express* x16 Riser Slot 1 Connector (J6A1)
124
Table 67. PCI Express* x16 Riser Slot 2 Connector (J1A3)
126
Table 68. PCI Express* x16 Riser Slot 3 Connector (J1H1)
128
7.4.2 VGA Connector
130
Table 69. PCI Express* Riser ID Assignment
130
Table 70. PCI Express* Clock Source by Slot
130
Table 71. VGA External Video Connector (J4A1)
130
NIC Connectors
131
SATA Connectors
131
Table 72. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA5A1)
131
Hard Drive Activity (Input) LED Header
132
Storage Upgrade Key Connector
132
Serial Port Connectors
132
Table 73. SATA Connector
132
Table 74. SATA HDD Activity (Input) LED Header (J6C5)
132
Table 75. Storage Upgrade Key Connector (J6C4)
132
Table 76. Internal 9-pin Serial A (COM1) (J6A2)
132
USB Connectors
133
QSFP for InfiniBand*
133
Table 77. External USB port Connector (J3A1)
133
Table 78. Internal USB Connector (J2D1)
133
Table 79. QSFP Pin Definition
133
Fan Headers
134
Chassis Intrusion
134
Table 80. Baseboard Fan Connector (J1K2)
134
Table 81. Chassis Intrusion Header (J6C1)
134
8. Intel Light-Guided Diagnostics
135
Front Panel Support
135
System ID LED
135
System Status LED
135
Network Link/Activity LED
135
Table 82. Network link/activity LED
135
Dedicated InfiniBand* Link/Activity LED
136
POST Code Diagnostic LEDs
136
Figure 47. Rear Panel Diagnostic LEDs (Block A)
136
Table 83. InfiniBand* link/activity LED
136
9. Environmental Limits Specification
137
System Level Environmental Considerations
137
Table 84. Server Board Design Specifications
137
Set Throttling Mode
138
Altitude
138
Set Fan Profile
138
Fan PWM Offset
138
Quiet Fan Idle Mode
138
Thermal Sensor Input for Fan Speed Control
139
Processor Thermal Design Power (TDP) Support
140
10. Power Supply Specification Guidelines
141
Power Supply DC Output Connector
141
Power Supply DC Output Specification
141
10.2.1 Output Power/Currents
141
10.2.2 Standby Output
141
10.2.3 Voltage Regulation
141
Table 85. Power Supply DC Power Input Connector Pin-out (See Table 60)
141
Table 86. Minimum Load Ratings
141
10.2.4 Dynamic Loading
142
10.2.5 Capacitive Loading
142
10.2.6 Grounding
142
10.2.7 Closed loop stability
142
10.2.8 Residual Voltage Immunity in Standby mode
142
Table 87. Voltage Regulation Limits
142
Table 88. Transient Load Requirements
142
Table 89. Capacitive Loading Conditions
142
10.2.9 Common Mode Noise
143
10.2.10 Soft Starting
143
10.2.11 Zero Load Stability Requirements
143
10.2.12 Hot Swap Requirements
143
10.2.13 Forced Load Sharing
143
10.2.14 Ripple/Noise
143
10.2.15 Timing Requirement
143
Table 90. Ripples and Noise
143
Table 91. Timing Requirements
144
Figure 48. Turn On/Off Timing (Power Supply Signals)
145
Appendix A: Integration and Usage Tips
146
Appendix B: Integrated BMC Sensor Tables
147
Table 92. BMC Sensor Table
149
Appendix C: BIOS Sensors and SEL Data
162
Table 93. BIOS Sensor and SEL Data
162
Appendix D: POST Code LED Decoder
169
Figure 49. Diagnostic LED Placement Diagram
169
Table 94. POST Progress Code LED Example
170
Table 95. Diagnostic LED POST Code Decoder
170
Appendix E: Video POST Code Errors
174
Table 96. POST Error Messages and Handling
174
Glossary
178
Table 97. Glossary
178
Reference Documents
181

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Intel S2600JFF マニュアル

ユーザーズマニュアル (BBS2600JFF)

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