データシート (HH80557KH0362M)目次1 Introduction91.1 Terminology91.1.1 Processor Terminology101.2 References112 Electrical Specifications132.1 Power and Ground Lands132.2 Decoupling Guidelines132.2.1 VCC Decoupling132.2.2 Vtt Decoupling132.2.3 FSB Decoupling142.3 Voltage Identification142.4 Market Segment Identification (MSID)162.5 Reserved, Unused, and TESTHI Signals162.6 Voltage and Current Specification172.6.1 Absolute Maximum and Minimum Ratings172.6.2 DC Voltage and Current Specification182.6.3 VCC Overshoot222.6.4 Die Voltage Validation222.7 Signaling Specifications232.7.1 FSB Signal Groups232.7.2 CMOS and Open Drain Signals252.7.3 Processor DC Specifications252.7.4 Clock Specifications272.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking272.7.6 FSB Frequency Select Signals (BSEL[2:0])282.7.7 Phase Lock Loop (PLL) and Filter282.7.8 BCLK[1:0] Specifications (CK505 based Platforms)292.7.9 BCLK[1:0] Specifications (CK410 based Platforms)302.8 PECI DC Specifications313 Package Mechanical Specifications333.1 Package Mechanical Drawing343.1.1 Processor Component Keep-Out Zones383.1.2 Package Loading Specifications383.1.3 Package Handling Guidelines383.1.4 Package Insertion Specifications383.1.5 Processor Mass Specification393.1.6 Processor Materials393.2 Processor Markings393.2.1 Processor Land Coordinates414 Land Listing and Signal Descriptions434.1 Processor Land Assignments434.2 Alphabetical Signals Reference665 Thermal Specifications and Design Considerations735.1 Processor Thermal Specifications735.1.1 Thermal Specifications735.1.2 Thermal Metrology785.2 Processor Thermal Features785.2.1 Thermal Monitor785.2.2 Thermal Monitor 2795.2.3 On-Demand Mode805.2.4 PROCHOT# Signal815.2.5 THERMTRIP# Signal815.3 Thermal Diode815.4 Platform Environment Control Interface (PECI)835.4.1 Introduction835.4.2 PECI Specifications866 Features876.1 Power-On Configuration Options876.2 Clock Control and Low Power States876.2.1 Normal State886.2.2 HALT and Extended HALT Powerdown States886.2.3 Stop Grant and Extended Stop Grant States896.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State906.3 Enhanced Intel® SpeedStep® Technology917 Boxed Processor Specifications937.1 Mechanical Specifications947.1.1 Boxed Processor Cooling Solution Dimensions947.1.2 Boxed Processor Fan Heatsink Weight957.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly957.2 Electrical Requirements957.2.1 Fan Heatsink Power Supply957.3 Thermal Specifications977.3.1 Boxed Processor Cooling Requirements977.3.2 Variable Speed Fan998 Debug Tools Specifications1018.1 Logic Analyzer Interface (LAI)1018.1.1 Mechanical Considerations1018.1.2 Electrical Considerations101サイズ： 2.35MBページ数： 102Language: Englishマニュアルを開く
データシート (SL9VT)目次1 Introduction91.1 Terminology91.1.1 Processor Terminology101.2 References112 Electrical Specifications132.1 Power and Ground Lands132.2 Decoupling Guidelines132.2.1 VCC Decoupling132.2.2 Vtt Decoupling132.2.3 FSB Decoupling142.3 Voltage Identification142.4 Market Segment Identification (MSID)162.5 Reserved, Unused, and TESTHI Signals162.6 Voltage and Current Specification172.6.1 Absolute Maximum and Minimum Ratings172.6.2 DC Voltage and Current Specification182.6.3 VCC Overshoot222.6.4 Die Voltage Validation222.7 Signaling Specifications232.7.1 FSB Signal Groups232.7.2 CMOS and Open Drain Signals252.7.3 Processor DC Specifications252.7.4 Clock Specifications272.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking272.7.6 FSB Frequency Select Signals (BSEL[2:0])282.7.7 Phase Lock Loop (PLL) and Filter282.7.8 BCLK[1:0] Specifications (CK505 based Platforms)292.7.9 BCLK[1:0] Specifications (CK410 based Platforms)302.8 PECI DC Specifications313 Package Mechanical Specifications333.1 Package Mechanical Drawing343.1.1 Processor Component Keep-Out Zones383.1.2 Package Loading Specifications383.1.3 Package Handling Guidelines383.1.4 Package Insertion Specifications383.1.5 Processor Mass Specification393.1.6 Processor Materials393.2 Processor Markings393.2.1 Processor Land Coordinates414 Land Listing and Signal Descriptions434.1 Processor Land Assignments434.2 Alphabetical Signals Reference665 Thermal Specifications and Design Considerations735.1 Processor Thermal Specifications735.1.1 Thermal Specifications735.1.2 Thermal Metrology785.2 Processor Thermal Features785.2.1 Thermal Monitor785.2.2 Thermal Monitor 2795.2.3 On-Demand Mode805.2.4 PROCHOT# Signal815.2.5 THERMTRIP# Signal815.3 Thermal Diode815.4 Platform Environment Control Interface (PECI)835.4.1 Introduction835.4.2 PECI Specifications866 Features876.1 Power-On Configuration Options876.2 Clock Control and Low Power States876.2.1 Normal State886.2.2 HALT and Extended HALT Powerdown States886.2.3 Stop Grant and Extended Stop Grant States896.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State906.3 Enhanced Intel® SpeedStep® Technology917 Boxed Processor Specifications937.1 Mechanical Specifications947.1.1 Boxed Processor Cooling Solution Dimensions947.1.2 Boxed Processor Fan Heatsink Weight957.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly957.2 Electrical Requirements957.2.1 Fan Heatsink Power Supply957.3 Thermal Specifications977.3.1 Boxed Processor Cooling Requirements977.3.2 Variable Speed Fan998 Debug Tools Specifications1018.1 Logic Analyzer Interface (LAI)1018.1.1 Mechanical Considerations1018.1.2 Electrical Considerations101サイズ： 2.35MBページ数： 102Language: Englishマニュアルを開く
