Jameco Electronics 3000 マニュアル

目次

• history

  1
• Z-World support

  1
• features

  1
• 1.1 Features and Specifications Rabbit 3000

  2
• block diagram

  5
• list of advantages

  6
• 1.3 Differences Rabbit 3000 vs. Rabbit 2000

  7
• design features

  9
• instruction set

  9
• interrupt priorities

  9
• memory support

  9
• design features

  9
• 2.1 The Rabbit 8-bit Processor vs. Other Processors

  10
• 2.2.1 5 V Tolerant Inputs

  11
• 2.2.2 Serial Ports

  11
• 5 V tolerant inputs

  11
• 5 V tolerant inputs

  11
• serial ports

  11
• on-chip peripherals

  11
• 2.2.3 System Clock

  12
• 2.2.4 32.768 kHz Oscillator Input

  12
• system clock

  12
• time/date clock

  12
• system clock

  12
• 2.2.5 Parallel I/O

  13
• parallel I/O

  13
• 2.2.6 Slave Port

  14
• 2.2.7 Auxiliary I/O Bus

  15
• 2.2.8 Timers

  15
• timers

  15
• 2.2.9 Input Capture Channels

  16
• input capture channels

  16
• 2.2.10 Quadrature Encoder Inputs

  17
• 2.2.11 Pulse Width Modulation Outputs

  17
• PWM outputs

  17
• quadrature encoder inputs

  17
• 2.2.12 Spread Spectrum Clock

  18
• 2.2.13 Separate Core and I/O Power Pins

  18
• 2.3.1 Programming Port

  18
• pins

  18
• programming port

  18
• 2.3.2 Standard BIOS

  19
• BIOS

  19
• 3.1 Processor Registers

  21
• registers

  21
• accumulators

  22
• alternate registers

  22
• index registers

  22
• stack pointer

  22
• status register

  22
• 3.2.1 Extended Code Space

  26
• XPC register

  26
• 3.2.2 Separate I and D Space - Extending Data Memory

  27
• 3.2.3 Using the Stack Segment for Data Storage

  29
• stack segment

  29
• 3.2.4 Practical Memory Considerations

  30
• practical considerations

  30
• 3.3.1 Load Immediate Data to a Register

  33
• 3.3.2 Load or Store Data from or to a Constant Address

  33
• load to register

  33
• 3.3.3 Load or Store Data Using an Index Register

  34
• 3.3.4 Register-to-Register Move

  35
• 3.3.5 Register Exchanges

  35
• register exchanges

  35
• 3.3.6 Push and Pop Instructions

  36
• 3.3.7 16-bit Arithmetic and Logical Ops

  36
• push and pop

  36
• 3.3.8 Input/Output Instructions

  39
• I/O instructions

  39
• 3.4.1 Zero HL in 4 Clocks

  40
• 3.4.2 Exchanges Not Directly Implemented

  40
• 3.4.3 Manipulation of Boolean Variables

  40
• 3.4.4 Comparisons of Integers

  41
• 3.4.5 Atomic Moves from Memory to I/O Space

  43
• 3.5 Interrupt Structure

  44
• 3.5.1 Interrupt Priority

  44
• interrupts

  44
• 3.5.2 Multiple External Interrupting Devices

  46
• 3.5.3 Privileged Instructions, Critical Sections and Semaphores

  46
• multiple interrupts

  46
• semaphores

  46
• 3.5.4 Critical Sections

  47
• 3.5.5 Semaphores Using Bit B,(HL)

  47
• semaphores

  47
• 3.5.6 Computed Long Calls and Jumps

  48
• 4.1 Precisely Timed Output Pulses

  49
• interrupt latency

  49
• timed output pulses

  49
• 4.1.1 Pulse Width Modulation to Reduce Relay Power

  50
• generating pulses

  50
• asynchronous I/O

  50
• open-drain outputs

  51
• open-drain outputs

  51
• 4.3 Cold Boot

  52
• cold boot

  52
• cold boot

  52
• 4.4.1 Slave Rabbit As A Protocol UART

  54
• 5.1 LQFP Package

  56
• 5.1.1 Pinout

  56
• pinout

  56
• LQFP package

  56
• 5.1.2 Mechanical Dimensions and Land Pattern

  57
• mechanical dimensions

  57
• LAND pattern

  58
• 5.2.1 Pinout

  59
• BGA package

  59
• 5.2.2 Mechanical Dimensions and Land Pattern

  60
• mechanical dimensions

  60
• pin descriptions

  62
• 5.4 Bus Timing

  64
• read and write timing

  64
• alternate functions

  65
• tions

  67
• 5.6 DC Characteristics

  68
• DC characteristics

  68
• ing limits

  69
• addresses

  72
• 6.1 Default Values for all the Peripheral Control Registers

  73
• default values

  73
• 7.1 Processor Identification

  79
• GRAM configuration

  79
• GROM configuration

  79
• GCSR

  82
• 7.3 Clock Doubler

  83
• GCDR

  83
• 7.5 Chip Select Options for Low Power

  87
• low-power options

  87
• GOCR

  90
• 7.7 Time/Date Clock (Real-Time Clock)

  91
• watchdog timer

  93
• WDTTR

  94
• 7.9 System Reset

  95
• 7.10.1 External Interrupts

  99
• external interrupts

  99
• 7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08

  100
• interrupt vectors

  100
• bootstrap operation

  101
• 7.12 Pulse Width Modulator

  103
• PWMxR

  103
• input capture

  105
• 7.14 Quadrature Decoder

  110
• quadrature decoder

  110
• Interface for Static Memory Chips

  115
• battery backup

  115
• SRAM

  115
• typical connections

  116
• Memory Mapping Overview

  117
• Memory-Mapping Unit

  117
• memory mapping

  117
• memory-mapping unit

  117
• ments

  118
• Memory Interface Unit

  119
• 8.5 Memory Bank Control Registers

  120
• MBxCR

  120
• memory bank control

  120
• 8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable)

  121
• enable)

  121
• memory timing

  122
• MECR

  122
• and data space

  123
• BDCR

  123
• ler

  123
• 8.7 Instruction and Data Space Support

  124
• support

  124
• compiler

  127
• parallel ports

  129
• 9.1 Parallel Port A

  130
• Parallel Port A

  130
• PADR

  130
• Parallel Port B

  131
• PBDDR

  131
• PBDR

  131
• 9.3 Parallel Port C

  132
• Parallel Port C

  132
• PCDR

  132
• PCFR

  132
• Parallel Port D

  133
• PDBxR

  133
• PDDCR

  133
• PDDDR

  133
• PDFR

  133
• 9.5 Parallel Port E

  137
• Parallel Port E

  137
• PEDDR

  138
• PEFR

  138
• Parallel Port F

  140
• 9.6.1 Using Parallel Port A and Parallel Port F

  141
• Parallel Port G

  143
• PGDR

  143
• PGFR

  143
• I/O bank control

  145
• timers

  149
• 11.1 Timer A

  150
• 11.1.1 Timer A I/O Registers

  151
• TATxR

  151
• 11.1.2 Practical Use of Timer A

  155
• TBCMR

  156
• Timer B

  156
• 11.2.1 Using Timer B

  159
• baud rates

  163
• 12.1 Serial Port Register Layout

  164
• registers

  164
• SCER

  166
• SCLR

  166
• SCSR

  166
• SACR

  166
• SAER

  166
• SBCR

  166
• SBLR

  166
• SBSR

  166
• SCDR

  166
• SDAR

  167
• SDCR

  167
• SDDR

  167
• SDLR

  167
• SDSR

  167
• SEAR

  167
• SECR

  167
• SEDR

  167
• SELR

  167
• SESR

  167
• SFAR

  167
• SFCR

  167
• SFER

  167
• SFLR

  167
• SFSR

  167
• ters

  168
• address registers

  168
• data registers

  168
• ters

  169
• status registers

  170
• registers

  171
• ports (A–D)

  171
• registers

  172
• (Ports E–F)

  172
• nous registers

  176
• registers

  176
• tended registers

  178
• ters (Ports E–F)

  178
• 12.3 Serial Port Interrupt

  179
• serial port

  179
• interrupts

  179
• 12.5 Receive Serial Data Timing

  181
• D)

  182
• 12.7 Clocked Serial Timing

  185
• 12.7.1 Clocked Serial Timing With Internal Clock

  185
• 12.7.2 Clocked Serial Timing with External Clock

  185
• clocked serial timing

  185
• munication

  187
• 12.9 Serial Port Software Suggestions

  192
• 12.9.1 Controlling an RS-485 Driver and Receiver

  193
• 12.9.2 Transmitting Dummy Characters

  193
• receiver

  193
• 12.9.3 Transmitting and Detecting a Break

  194
• 12.9.4 Using A Serial Port to Generate a Periodic Interrupt

  194
• 12.9.5 Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes

  194
• extra stop bits, parity

  194
• periodic interrupts

  194
• 12.9.6 Parity, Extra Stop Bits with 7-Data-Bit Characters

  195
• 12.9.7 Parity, Extra Stop Bits with 8-Data-Bit Characters

  195
• 12.9.8 Supporting 9th Bit Communication Protocols

  196
• 12.9.9 Rabbit-Only Master/Slave Protocol

  196
• 12.9.10 Data Framing/Modbus

  196
• Modbus

  196
• 9th bit protocols

  196
• master/slave protocol

  196
• Rabbit slave port

  199
• R/W cycles

  200
• slave port lines

  203
• typical connections

  203
• 13.1 Hardware Design of Slave Port Interconnection

  204
• slave port registers

  204
• SPDxR

  204
• hardware design

  204
• registers

  204
• 13.3 Applications and Communications Protocols for Slaves

  206
• 13.3.1 Slave Applications

  206
• applications

  206
• protocols

  206
• 13.3.2 Master-Slave Messaging Protocol

  207
• messaging protocol

  207
• oscillator circuits

  209
• oscillator

  209
• main oscillator

  209
• 14.1 Low-Power Design

  210
• low-power design

  210
• low-power design

  210
• EMI mitigation

  211
• 15.1 Power Supply Connections and Board Layout

  212
• PCB layout

  212
• spectrum spreader

  212
• EMI mitigation

  212
• registers

  213
• 16.1 Memory Access Time

  215
• doubler

  221
• I/O access time

  223
• I/O read time delays

  224
• 16.3 Further Discussion of Bus and Clock Timing

  225
• 16.5 Power and Current Consumption

  229
• power consumption

  229
• mechanisms

  232
• 16.7 Sleepy Mode Current Consumption

  233
• memory

  234
• 16.9 Battery-Backed Clock Current Consumption

  235
• 17.1 The BIOS

  237
• 17.1.1 BIOS Services

  237
• BIOS

  237
• 17.1.2 BIOS Assumptions

  238
• 17.2.1 Periodic Interrupt

  238
• 17.2.2 Watchdog Timer Support

  238
• Dynamic C

  238
• periodic interrupts

  238
• virtual drivers

  238
• watchdog

  238
• 18.1 Power Management Support

  241
• power consumption

  241
• Dynamic C

  241
• power management

  241
• 18.2.1 Using Assembly Language

  242
• 18.2.2 Using Library Functions

  242
• ters

  242
• library functions

  242
• 18.3.1 Updating Shadow Registers

  243
• 18.3.2 Interrupt While Updating Registers

  243
• updating registers

  243
• shadow registers

  243
• 18.3.3 Write-only Registers Without Shadow Registers

  244
• 19.1 Load Immediate Data

  250
• 19.3 8-bit Indexed Load and Store

  250
• 19.5 16-bit Load and Store 20-bit Address

  251
• 19.7 Exchange Instructions

  252
• 19.9 16-bit Arithmetic and Logical Ops

  252
• 19.11 8-bit Bit Set, Reset and Test

  254
• 19.13 8-bit Fast A Register Operations

  255
• 19.15 Instruction Prefixes

  256
• Block Move Instructions

  256
• Control Instructions - Jumps and Calls

  257
• Miscellaneous Instructions

  257
• Privileged Instructions

  258
• Rabbit 2000

  259
• alphabetic order

  261
• programming port

  269
• programing port

  269
• A.1 Use of the Programming Port as a Diagnostic/Setup Port

  270
• use as diagnostic port

  270
• A.3 Suggested Rabbit Crystal Frequencies

  271
• crystal frequencies

  271
• crystal frequencies

  271
• B.1 Discussion of Fixes and Improvements

  276
• als

  276
• ty

  276
• ments

  276
• IrDA bug fix

  276
• bug fix

  276
• memory protection

  276
• subtract

  276
• Port A decode bug fix

  276
• PWM improvements

  276
• ments

  276
• stack protection

  276
• System/User mode

  276
• codes

  276
• B.1.1 Rabbit Internal I/O Registers

  277
• internal I/O registers

  277
• B.1.2 Peripheral and ISR Address

  280
• B.1.3 Revision-Level ID Register

  282
• revision-level ID

  282
• B.1.4 System/User Mode

  283
• B.1.5 Memory Protection

  284
• memory protection

  284
• WPCR

  284
• WPLR

  284
• WPHR

  285
• WPSxR

  286
• WPxLR

  286
• WPxHR

  287
• B.1.6 Stack Protection

  289
• stack protection

  289
• STKCR

  290
• STKHLR

  290
• STKLLR

  290
• B.1.7 RAM Segment Relocation

  291
• RAMSR

  291
• B.1.8 Secondary Watchdog Timer

  292
• SWDTR

  292
• B.1.9 New Opcodes

  293
• opcodes

  293
• opcodes

  293
• B.1.10 Expanded I/O Memory Addressing

  295
• B.1.11 External I/O Improvements

  296
• B.1.12 Short Chip Select Timing for Writes

  297
• GSCR

  298
• B.1.13 Pulse Width Modulator Improvements

  311
• PWL0R

  312
• PWL1R

  312
• PWL2R, PWL3R

  312
• B.1.14 Quadrature Decoder Improvements

  314
• QDCxHR

  314
• quadrature decoder

  315
• tions

  316
• C.1 System/User Mode Opcodes

  318
• MB0CR

  319
• System/User mode

  319
• registers

  319
• I/O addresses

  320
• C.3 Interrupts

  321
• System/User mode

  321
• interrupts

  321
• C.3.1 Peripheral Interrupt Prioritization

  322
• C.4.1 Memory Protection Only

  324
• use

  324
• memory protection

  324
• C.4.2 Mixed System/User Mode Operation

  325
• mixed operation

  325
• C.4.3 Complete Operating System

  326
• tem

  326
• internal I/O registers

  327