データシート目次1.0 Electrical Characteristics3FIGURE 1-1: Serial Output Timing Diagram.7FIGURE 1-2: Serial Input Timing Diagram.7FIGURE 1-3: Data Ready Pulse Timing Diagram.8FIGURE 1-4: Specific Timing Diagrams.8FIGURE 1-5: MCP3901 Clock Detail.82.0 Typical Performance Curves9FIGURE 2-1: Spectral Response.9FIGURE 2-2: Spectral Response.9FIGURE 2-3: Spectral Response.9FIGURE 2-4: Spectral Response.9FIGURE 2-5: Spectral Response.9FIGURE 2-6: Spectral Response.9FIGURE 2-7: Spectral Response.10FIGURE 2-8: Spectral Response.10FIGURE 2-9: Spurious Free Dynamic Range Histogram.10FIGURE 2-10: Spurious Free Dynamic Range vs. Oversampling Ratio.10FIGURE 2-11: Signal-to-Noise and Distortion and Effective Number of Bits vs. Oversampling Ratio.10FIGURE 2-12: Signal-to-Noise and Distortion vs. Gain.10FIGURE 2-13: Signal-to-Noise and Distortion vs. Gain (Dithering On).11FIGURE 2-14: Total Harmonic Distortion vs. Oversampling Ratio.11FIGURE 2-15: Total Harmonic Distortion vs. Input Signal Frequency.11FIGURE 2-16: Total Harmonic Distortion Histogram (Dithering On).11FIGURE 2-17: Total Harmonic Distortion vs. Temperature.11FIGURE 2-18: Signal-to-Noise and Distortion vs. Input Frequency.11FIGURE 2-19: Signal-to-Noise and Distortion Histogram.12FIGURE 2-20: Signal-to-Noise and Distortion vs. Temperature.12FIGURE 2-21: Signal-to-Noise and Distortion vs. Input Signal Amplitude.12FIGURE 2-22: Channel 0 Offset vs. Temperature.12FIGURE 2-23: Channel 1 Offset vs. Temperature.12FIGURE 2-24: Channel-to-Channel Offset Match vs. Temperature.12FIGURE 2-25: Positive Gain Error vs. Temperature.13FIGURE 2-26: Negative Gain Error vs. Temperature13FIGURE 2-27: Internal Voltage Reference vs. Temperature.13FIGURE 2-28: Internal Voltage Reference vs. Supply Voltage.13FIGURE 2-29: Signal-to-Noise and Distortion vs. Master Clock (MCLK), BOOST ON.13FIGURE 2-30: Noise Histogram.13FIGURE 2-31: Integral Nonlinearity (Dithering Off).14FIGURE 2-32: Integral Nonlinearity (Dithering On).14FIGURE 2-33: Operating Current vs. Master Clock (MCLK).143.0 Pin Description15TABLE 3-1: Pin Function Table153.1 RESET153.2 Digital VDD (DVDD)153.3 Analog VDD (AVDD)153.4 ADC Differential Analog inputs (CHn+/CHn-)163.5 Analog Ground (AGND)163.6 Non-Inverting Reference Input, Internal Reference Output (REFIN+/OUT)163.7 Inverting Reference Input (REFIN-)163.8 Digital Ground Connection (DGND)163.9 Modulator Data Output Pin for Channel 1 and Channel 0 (MDAT1/MDAT0)163.10 DR (Data Ready Pin)163.11 Oscillator and Master Clock Input Pins (OSC1/CLKI, OSC2)173.12 CS (Chip Select)173.13 SCK (Serial Data Clock)173.14 SDO (Serial Data Output)173.15 SDI (Serial Data Input)174.0 Terminology And Formulas194.1 MCLK – Master Clock194.2 AMCLK – Analog Master Clock19TABLE 4-1: MCP3901 OVERSAMPLING RATIO SETTINGS194.3 DMCLK – Digital Master Clock194.4 DRCLK – Data Rate Clock19TABLE 4-2: Device data rates in function of mclk, osr AND PRESCALE204.5 Oversampling Ratio (OSR)20TABLE 4-3: MCP3901 OVERSAMPLING RATIO SETTINGS204.6 Offset Error204.7 Gain Error204.8 Integral Nonlinearity Error214.9 Signal-to-Noise Ratio (SNR)214.10 Signal-to-Noise Ratio And Distortion (SINAD)214.11 Total Harmonic Distortion (THD)214.12 Spurious-Free Dynamic Range (SFDR)214.13 MCP3901 Delta-Sigma Architecture224.14 Idle Tones224.15 Dithering224.16 Crosstalk234.17 PSRR234.18 CMRR234.19 ADC Reset Mode234.20 Hard Reset Mode (RESET = 0)244.21 ADC Shutdown Mode244.22 Full Shutdown Mode245.0 Device Overview255.1 Analog Inputs (CHn+/-)255.2 Programmable Gain Amplifiers (PGA)25TABLE 5-1: pga configuration Setting255.3 Delta-Sigma Modulator25FIGURE 5-1: Simplified Delta-Sigma ADC Block Diagram.255.4 Modulator Output Block26TABLE 5-2: Delta-sigma modulator coding26FIGURE 5-2: MDAT Serial Outputs in Function of the Modulator Output Code.265.5 SINC3 Filter27TABLE 5-3: adc RESOLUTION vs. osr27FIGURE 5-3: SINC Filter Response with MCLK = 4 MHz, OSR = 64, PRESCALE = 1.275.6 ADC Output Coding28TABLE 5-4: OSR = 256 output code examples28TABLE 5-5: OSR = 128 output code examples28TABLE 5-6: OSR = 64 output code examples29TABLE 5-7: OSR = 32 output code examples295.7 Voltage Reference295.8 Power-on Reset30FIGURE 5-4: Power-on Reset Operation.305.9 RESET Effect on Delta-Sigma Modulator/SINC Filter305.10 Phase Delay Block30TABLE 5-8: Phase Values With MCLK = 4 MHz, OSR = 256315.11 Crystal Oscillator316.0 Serial Interface Description336.1 Overview336.2 Control Byte33FIGURE 6-1: Control Byte.336.3 Reading from the Device336.4 Writing to the Device336.5 SPI MODE 1,1 – Clock Idle High, Read/Write Examples33FIGURE 6-2: Device Read (SPI Mode 1,1 – Clock Idles High).34FIGURE 6-3: Device Write (SPI Mode 1,1 – Clock Idles High).346.6 SPI MODE 0,0 – Clock Idle Low, Read/Write Examples35FIGURE 6-4: Device Read (SPI Mode 0,0 – Clock Idles Low).35FIGURE 6-5: Device Write (SPI Mode 0,0 – Clock Idles Low).356.7 Continuous Communication, Looping on Address Sets36FIGURE 6-6: Typical Continuous Read Communication.36TABLE 6-1: Register Groups37TABLE 6-2: Register Types376.8 Situations that Reset ADC Data37FIGURE 6-7: Recommended Configuration Sequence at Power-up.376.9 Data Ready Pin (DR)386.10 Data Ready Latches and Data Ready Modes (DRMODE<1:0>)38FIGURE 6-8: Data Ready Behavior.407.0 Internal Registers41TABLE 7-1: Register map41TABLE 7-2: Register Map Grouping for Continuous read modes417.1 ADC Channel Data Output Registers427.2 Modulator Output Register437.3 PHASE Register447.4 Gain Configuration Register457.5 Status and Communication Register467.6 Configuration Registers488.0 Packaging Information518.1 Package Marking Information51Corporate Office62Atlanta62Boston62Chicago62Cleveland62Fax: 216-447-064362Dallas62Detroit62Indianapolis62Toronto62Fax: 852-2401-343162Australia - Sydney62China - Beijing62China - Shanghai62India - Bangalore62Korea - Daegu62Korea - Seoul62Singapore62Taiwan - Taipei62Fax: 43-7242-2244-39362Denmark - Copenhagen62France - Paris62Germany - Munich62Italy - Milan62Spain - Madrid62UK - Wokingham62Worldwide Sales and Service62Trademarks61Worldwide Sales and Service62サイズ： 1.75MBページ数： 62Language: Englishマニュアルを開く
ユーザーズマニュアル目次Trademarks2Table of Contents3Preface7Document Revision History10Chapter 1. Product Overview111.1 Introduction111.2 What the MCP3901 and PIC18F65J90 Energy Meter Reference Design Kit Includes121.3 Getting Started12Chapter 2. Hardware132.1 Overview132.2 Input and Analog Front End16Chapter 3. Calculation Engine and Register Description173.1 Calculation Engine Signal Flow Summary173.2 Register List183.3 MODE193.4 STATUS203.5 CAL_CONTROL203.6 LINE_CYC213.7 LINE_CYC_CNT213.8 RAW2_I_RMS213.9 RAW_I_RMS223.10 I_RMS223.11 RAW2_V_RMS223.12 RAW_V_RMS223.13 V_RMS223.14 LINE_FREQUENCY233.15 RAW_POWER_ACT233.16 POWER_ACT233.17 POWER_APP233.18 RAW_POWER_REACT243.19 POWER_REACT243.20 PERIOD243.21 ENERGY_ACT243.22 ENERGY_APP253.23 I_ABS_MAX253.24 V_ABS_MAX253.25 ENERGY_REACT253.26 PHASE_COMPENSATION253.27 OFFSET_I_RMS263.28 OFFSET_V_RMS263.29 GAIN_I_RMS263.30 GAIN_V_RMS263.31 OFFSET_POWER_ACT263.32 GAIN_POWER_ACT273.33 OFFSET_POWER_REACT273.34 GAIN_POWER_REACT273.35 GAIN_ENERGY_ACT273.36 GAIN_ENERGY_APP273.37 GAIN_ENERGY_REACT273.38 CF_PULSE_WIDTH283.39 GAIN_DENR_ENERGY_ACT283.40 GAIN_NUMR_ENERGY_ACT283.41 MODE1_DEF283.42 CAL_STATUS283.43 MAXIMUM CURRENT293.44 CALIBRATION_VOLTAGE293.45 CALIBRATION_CURRENT293.46 CALIBRATION_FREQUENCY293.47 METER_CONSTANT293.48 CALIBRATION_LINE_CYCLE303.49 GAIN_DENR_ENERGY_REACT303.50 GAIN_NUMR_ENERGY_REACT303.51 PHASE_COMPENSATION_90303.52 CREEP_THRSHOLD_MINUTE303.53 CREEP_THRSHOLD_SECOND30Chapter 4. Meter Protocol and Timings314.1 Protocol31Appendix A. Schematic and Layouts33A.1 Introduction33A.2 Schematics and PCB Layout33A.3 Board – ADC Schematic34A.4 Board – MCU Schematic35A.5 Board – LCD and USB Schematic36A.6 Board – Top Silk and Pads37A.7 Board – Top Copper38A.8 Board – Bottom Copper39A.9 Board – Bottom Silk and Pads40A.10 Board – Top 3D41A.11 Board – Bottom 3D42Appendix B. Bill of Materials (BOM)43Worldwide Sales and Service46サイズ： 1.98MBページ数： 46Language: Englishマニュアルを開く
