ユーザーズマニュアル目次Table of Contents3Preface5Introduction5Document Layout6Conventions Used in this Guide7Documentation Conventions7The Microchip Web Site8Recommended Reading8Development Systems Customer Change Notification Service9Warranty Registration9Customer Support10Document Revision History10Chapter 1. Introduction to the PICDEM MC LV Development Board111.1 Introduction111.2 Highlights111.3 Motor Control Kit111.4 Overview of the PICDEM MC LV Development Board111.5 Board Connectors12Figure 1-1: Board Layout121.5.1 Power Connector (J20)131.5.2 Motor Connector (J9)13Table 1-1: Terminal Functionality131.5.3 ICD 2 Connector (J6)131.5.4 Serial Interface (RS-232) Connector (J1)13Chapter 2. System Level Architecture of the Board152.1 Highlights152.2 Board Block Diagram15Figure 2-1: Block Diagram152.3 Control Section162.3.1 Controller Sockets162.3.2 Overcurrent Protection Circuit162.3.3 User Interface16Table 2-1: User Interface162.3.4 Hall Sensor Interface172.3.5 Back EMF Signal Conditioning172.3.6 Temperature Measurement Circuit172.4 Power Inverter Section17Figure 2-2: Half-Bridge Gate Driver and Inverter172.5 Power Supply182.5.1 Connecting an Alternate Power Supply18Chapter 3. Getting Started with PIC18FXX31 MCUs193.1 Introduction193.2 Highlights193.3 PICDEM MC LV Development Board Setup19Table 3-1: Jumper Settings20Table 3-2: Motor Connections20Chapter 4. Using the Microchip Motor Control GUI214.1 Highlights214.2 Software Overview214.3 Starting the Program21Figure 4-1: The Control Panel View224.4 The Main Window (Control Panel)224.5 The Setup Window24Figure 4-2: Typical Setup Window244.5.1 Motor Parameters244.5.2 System Parameters254.5.3 System Limits254.5.4 Storing and Using Setting Profiles26Chapter 5. Creating Motor Control Firmware Projects275.1 Highlights275.2 Included Applications275.3 Beyond the Included Applications: Creating New Projects27Chapter 6. Getting Started with dsPIC Digital Signal Controllers296.1 Highlights296.2 Initial Setup29Table 6-1: Jumper Settings30Table 6-2: Motor Connections30Chapter 7. Using dsPIC DSCs to Run a Sensorless BLDC Motor317.1 Introduction317.2 Highlights317.3 Sensorless Control of a BLDC Motor31Figure 7-1: Zero-Crossing Detection31Figure 7-2: Hardware Block Diagram327.4 Using the PICDEM MC LV Development Board for Higher Motor Voltage337.5 Using the PICDEM MC LV Development Board for Lower Motor Voltage33Chapter 8. Troubleshooting358.1 Highlights358.2 Common Problems358.2.1 The Power LED D7 is Not Lit358.2.2 The Motor Control GUI Cannot Communicate with the Board358.2.3 The Motor Does Not Start When S2 or S3 is Pressed368.2.4 A Fault Condition Occurs While Accelerating the Motor368.2.5 A Fault Condition Occurs When the Motor is Loaded36Appendix A. Circuit Schematics of the Board37Figure A-1: Circuit Schematic (Sheet 1 of 2)37Figure A-2: Circuit Schematic (Sheet 2 of 2)38Appendix B. Electrical Specifications39Table B-1: DC Input Rating39Table B-2: Output Rating39Appendix C. Jumper Settings41Table C-1: Jumper Settings41Index43Worldwide Sales and Service46サイズ： 1.08MBページ数： 46Language: Englishマニュアルを開く
データシート目次14-Bit Power Control PWM Module:3Motion Feedback Module:3High-Speed, 200 ksps 10-Bit A/D Converter:3Flexible Oscillator Structure:3Power-Managed Modes:3Peripheral Highlights:3Special Microcontroller Features:3Pin Diagrams4Pin Diagrams (Continued)5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Table of Contents8Most Current Data Sheet9Errata9Customer Notification System91.0 Device Overview111.1 New Core Features111.1.1 nanoWATT Technology111.1.2 Multiple Oscillator Options and Features111.2 Other Special Features121.3 Details on Individual Family Members13TABLE 1-1: Device Features13FIGURE 1-1: PIC18F2331/2431 (28-pin) Block Diagram14FIGURE 1-2: PIC18F4331/4431 (40/44-pin) Block Diagram15TABLE 1-2: PIC18F2331/2431 Pinout I/O Descriptions16TABLE 1-3: PIC18F4331/4431 Pinout I/O Descriptions192.0 Guidelines for Getting Started with PIC18F Microcontrollers252.1 Basic Connection Requirements25FIGURE 2-1: Recommended Minimum connections252.2 Power Supply Pins262.2.1 Decoupling Capacitors262.2.2 Tank Capacitors262.2.3 Considerations When Using BOR262.3 Master Clear (MCLR) Pin27FIGURE 2-2: Example of MCLR Pin Connections272.4 ICSP Pins272.5 External Oscillator Pins282.6 Unused I/Os28FIGURE 2-3: Suggested Placement of the Oscillator Circuit283.0 Oscillator Configurations293.1 Oscillator Types293.2 Crystal Oscillator/Ceramic Resonators29FIGURE 3-1: Crystal/Ceramic Resonator Operation (XT, LP, HS or HSPLL Configuration)29TABLE 3-1: Capacitor Selection for Ceramic Resonators29TABLE 3-2: Capacitor Selection for Crystal Oscillator30FIGURE 3-2: External Clock Input Operation (HS Osc Configuration)303.3 PLL Frequency Multiplier303.3.1 HSPLL OSCILLATOR MODE30FIGURE 3-3: PLL Block Diagram303.4 External Clock Input31FIGURE 3-4: External Clock Input Operation (EC Configuration)31FIGURE 3-5: External Clock Input Operation (ECIO Configuration)313.5 RC Oscillator31FIGURE 3-6: RC Oscillator Mode31FIGURE 3-7: RCIO Oscillator Mode313.6 Internal Oscillator Block323.6.1 INTIO Modes323.6.2 INTRC Output Frequency323.6.3 OSCTUNE Register323.6.4 INTOSC Frequency Drift32Register 3-1: OSCTUNE: Oscillator Tuning Register333.7 Clock Sources and Oscillator Switching343.7.1 Oscillator Control Register34FIGURE 3-8: PIC18F2331/2431/4331/4431 Clock Diagram35Register 3-2: OSCCON: Oscillator Control Register363.7.2 Oscillator Transitions373.8 Effects of Power-Managed Modes on the Various Clock Sources373.9 Power-up Delays37TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode374.0 Power-Managed Modes394.1 Selecting Power-Managed Modes394.1.1 Clock Sources394.1.2 Entering Power-Managed Modes39TABLE 4-1: Power-Managed Modes394.1.3 Clock Transitions and Status Indicators404.1.4 Multiple Sleep Commands404.2 Run Modes404.2.1 PRI_RUN Mode404.2.2 SEC_RUN Mode40FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode41FIGURE 4-2: Transition Timing from SEC_RUN Mode to PRI_RUN Mode (HSPLL)414.2.3 RC_RUN Mode41FIGURE 4-3: Transition Timing to RC_RUN Mode42FIGURE 4-4: Transition Timing from RC_RUN Mode to PRI_RUN Mode424.3 Sleep Mode434.4 Idle Modes43FIGURE 4-5: Transition Timing for Entry to Sleep Mode43FIGURE 4-6: Transition Timing for Wake from Sleep (HSPLL)434.4.1 PRI_IDLE Mode444.4.2 SEC_IDLE Mode44FIGURE 4-7: Transition Timing for Entry to Idle Mode44FIGURE 4-8: Transition Timing for Wake from Idle to Run Mode444.4.3 RC_IDLE Mode454.5 Exiting Idle and Sleep Modes454.5.1 Exit By Interrupt454.5.2 Exit By WDT Time-out454.5.3 Exit By Reset454.5.4 Exit Without an Oscillator Start-up Delay46TABLE 4-2: Exit Delay on Wake-up By Reset from Sleep Mode or Any Idle Mode (By Clock Sources)465.0 Reset47FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit475.1 RCON Register48Register 5-1: RCON: Reset Control Register485.2 Master Clear (MCLR)495.3 Power-on Reset (POR)49FIGURE 5-2: External Power-on Reset Circuit (For Slow Vdd Power-up)495.4 Brown-out Reset (BOR)495.5 Device Reset Timers505.5.1 POWER-UP TIMER (PWRT)505.5.2 OSCILLATOR START-UP TIMER (OST)505.5.3 PLL LOCK TIME-OUT505.5.4 TIME-OUT SEQUENCE50TABLE 5-1: Time-out in Various Situations505.6 Reset State of Registers51FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)51FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 151FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 252FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)52FIGURE 5-7: Time-out Sequence on POR w/PLL Enabled (MCLR Tied to Vdd)53TABLE 5-2: Status Bits, Their Significance and the Initialization Condition for RCON Register53TABLE 5-3: Initialization Conditions for All Registers546.0 Memory Organization61FIGURE 6-1: Program Memory Map and Stack for PIC18F2331/4331616.1 Program Memory Organization61FIGURE 6-2: Program Memory Map and Stack for PIC18F2431/4431616.1.1 Program Counter626.1.2 Return Address Stack62FIGURE 6-3: Return Address Stack and Associated Registers63Register 6-1: STKPTR: Stack Pointer Register636.1.3 Fast Register Stack64EXAMPLE 6-1: Fast Register Stack Code Example646.1.4 Look-Up Tables in Program Memory64EXAMPLE 6-2: Computed GOTO Using an Offset Value646.2 Clocking Scheme/Instruction Cycle65FIGURE 6-4: Clock/ Instruction Cycle656.3 Instruction Flow/Pipelining65EXAMPLE 6-3: Instruction Pipeline Flow656.4 Instructions in Program Memory666.4.1 Two-Word Instructions66FIGURE 6-5: Instructions in Program Memory66EXAMPLE 6-4: Two-Word Instructions666.5 Data Memory Organization67FIGURE 6-6: Data Memory Map for PIC18F2331/2431/4331/4431 Devices676.5.1 Bank Select Register (BSR)686.5.2 Access Bank686.5.3 GENERAL PURPOSE REGISTER (GPR) FILE686.5.4 Special Function Registers69TABLE 6-1: Special Function Register Map for PIC18F2331/2431/4331/4431 Devices69TABLE 6-2: Register File Summary (PIC18F2331/2431/4331/4431)706.6 STATUS Register74Register 6-2: Status Register746.7 Data Addressing Modes756.7.1 Inherent and Literal Addressing756.7.2 Direct Addressing756.7.3 Indirect Addressing75EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing75FIGURE 6-7: Indirect Addressing767.0 Data EEPROM Memory797.1 EEADR797.2 EECON1 and EECON2 Registers79Register 7-1: EECON1: EEPROM Control Register 1807.3 Reading the Data EEPROM Memory817.4 Writing to the Data EEPROM Memory817.5 Write Verify817.6 Protection Against Spurious Write81EXAMPLE 7-1: Data EEPROM Read81EXAMPLE 7-2: Data EEPROM Write817.7 Operation During Code-Protect827.8 Protection Against Spurious Write827.9 Using the Data EEPROM82EXAMPLE 7-3: Data EEPROM Refresh Routine82TABLE 7-1: Registers Associated with Data EEPROM Memory838.0 Flash Program Memory858.1 Table Reads and Table Writes85FIGURE 8-1: Table Read Operation85FIGURE 8-2: Table Write Operation868.2 Control Registers868.2.1 EECON1 and EECON2 Registers86Register 8-1: EECON1: Data EEPROM Control Register 1878.2.2 TABLAT – Table Latch Register888.2.3 TBLPTR – Table Pointer Register888.2.4 Table Pointer Boundaries88TABLE 8-1: Table Pointer Operations with TBLRD and TBLWT Instructions88FIGURE 8-3: Table Pointer Boundaries Based on Operation888.3 Reading the Flash Program Memory89FIGURE 8-4: Reads From Flash Program Memory89EXAMPLE 8-1: Reading a Flash Program Memory Word898.4 Erasing Flash Program Memory908.4.1 Flash Program Memory Erase Sequence90EXAMPLE 8-2: Erasing a Flash Program Memory Row908.5 Writing to Flash Program Memory91FIGURE 8-5: Table Writes to Flash Program Memory918.5.1 Flash Program Memory Write Sequence92EXAMPLE 8-3: Writing to Flash Program Memory93EXAMPLE 8-3: Writing to Flash Program Memory (Continued)948.5.2 Write Verify948.5.3 Unexpected Termination of Write Operation948.6 Flash Program Operation During Code Protection94TABLE 8-2: Registers Associated with Program Flash Memory949.0 8 x 8 Hardware Multiplier959.1 Introduction959.2 Operation95EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine95EXAMPLE 9-2: 8 x 8 Signed Multiply Routine95TABLE 9-1: Performance Comparison95EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm96EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine96EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm96EXAMPLE 9-4: 16 x 16 Signed Multiply Routine9610.0 Interrupts97FIGURE 10-1: Interrupt Logic9810.1 INTCON Registers99Register 10-1: INTCON: Interrupt Control Register99Register 10-2: INTCON2: Interrupt Control Register 2100Register 10-3: INTCON3: Interrupt Control Register 310110.2 PIR Registers102Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1102Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2103Register 10-6: PIR3: Peripheral Interrupt Request (Flag) Register 310410.3 PIE Registers105Register 10-7: PIE1: Peripheral Interrupt Enable Register 1105Register 10-8: PIE2: Peripheral Interrupt Enable Register 2106Register 10-9: PIE3: Peripheral Interrupt Enable Register 310710.4 IPR Registers108Register 10-10: IPR1: Peripheral Interrupt Priority Register 1108Register 10-11: IPR2: Peripheral Interrupt Priority Register 2109Register 10-12: IPR3: Peripheral Interrupt Priority Register 311010.5 RCON Register111Register 10-13: RCON: Reset Control Register11110.6 INTx Pin Interrupts11210.7 TMR0 Interrupt11210.8 PORTB Interrupt-on-Change11210.9 Context Saving During Interrupts112EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM11211.0 I/O Ports113FIGURE 11-1: Generic I/o Port operation11311.1 PORTA, TRISA and LATA Registers113EXAMPLE 11-1: Initializing PORTA113TABLE 11-1: PORTA I/O Summary114TABLE 11-2: Summary of Registers Associated with PORTA11511.2 PORTB, TRISB and LATB Registers116EXAMPLE 11-2: Initializing PORTB116TABLE 11-3: PORTB I/O Summary117TABLE 11-4: Summary of Registers Associated with PORTB11811.3 PORTC, TRISC and LATC Registers119EXAMPLE 11-3: Initializing PORTC119TABLE 11-5: PORTC I/O Summary120TABLE 11-6: Summary of Registers Associated with PORTC12111.4 PORTD, TRISD and LATD Registers122EXAMPLE 11-4: Initializing PORTD122TABLE 11-7: PORTD I/O Summary123TABLE 11-8: Summary of Registers Associated with PORTD12311.5 PORTE, TRISE and LATE Registers124EXAMPLE 11-5: Initializing PORTE12411.5.1 PORTE in 28-pIN Devices124Register 11-1: TRISE Register124TABLE 11-9: PORTE I/O Summary125TABLE 11-10: Summary of Registers Associated with PORTE12512.0 Timer0 Module127Register 12-1: T0CON: Timer0 Control Register127FIGURE 12-1: Timer0 Block Diagram (8-Bit Mode)128FIGURE 12-2: Timer0 Block Diagram (16-Bit Mode)12812.1 Timer0 Operation12912.2 Prescaler12912.2.1 Switching Prescaler Assignment12912.3 Timer0 Interrupt12912.4 16-Bit Mode Timer Reads and Writes129TABLE 12-1: Registers Associated with Timer012913.0 Timer1 Module131Register 13-1: T1CON: Timer1 Control Register13113.1 Timer1 Operation132FIGURE 13-1: Timer1 Block Diagram132FIGURE 13-2: Timer1 Block Diagram (16-Bit Read/Write Mode)13213.2 Timer1 Oscillator133FIGURE 13-3: External Components for the Timer1 LP Oscillator133TABLE 13-1: Capacitor Selection for the Timer Oscillator13313.3 Timer1 Oscillator Layout Considerations13313.4 Timer1 Interrupt13413.5 Resetting Timer1 Using a CCP Trigger Output13413.6 Timer1 16-Bit Read/Write Mode13413.7 Using Timer1 as a Real-Time Clock (RTC)134EXAMPLE 13-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service135TABLE 13-2: Registers Associated with Timer1 as a Timer/Counter13514.0 Timer2 Module13614.1 Timer2 Operation136Register 14-1: T2CON: Timer2 Control Register13614.2 Timer2 Interrupt13714.3 Output of TMR2137FIGURE 14-1: Timer2 Block Diagram137TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter13715.0 Timer5 Module139Register 15-1: T5CON: Timer5 Control Register139FIGURE 15-1: Timer5 Block Diagram (16-bit Read/Write Mode Shown)14015.1 Timer5 Operation14015.1.1 Continuous Count and Single-Shot Operation14115.2 16-Bit Read/Write and Write Modes14115.2.1 16-bit Read-Modify-Write14115.3 Timer5 Prescaler14115.4 Noise Filter14215.5 Timer5 Interrupt14215.6 Timer5 Special Event Trigger Output14215.7 Timer5 Special Event Trigger Reset Input14215.7.1 Wake-up on IC1 Edge14215.7.2 Delayed Action Event Trigger14215.7.3 Special Event Trigger Reset While Timer5 Is Incrementing14215.8 Operation in Sleep Mode14215.8.1 Interrupt Detect in Sleep Mode142TABLE 15-1: Registers Associated with Timer514316.0 Capture/Compare/PWM (CCP) Modules14516.1 CCP1 Module145TABLE 16-1: CCP Mode – Timer Resources14516.2 CCP2 Module145Register 16-1: CCPxCON: CCPx Control Register14516.3 Capture Mode14616.3.1 CCP Pin Configuration14616.3.2 Timer1 Mode Selection14616.3.3 Software Interrupt14616.3.4 CCP Prescaler146EXAMPLE 16-1: Changing Between Capture Prescalers146FIGURE 16-1: Capture Mode Operation Block Diagram14616.4 Compare Mode14716.4.1 CCP Pin Configuration14716.4.2 Timer1 Mode Selection14716.4.3 Software Interrupt Mode14716.4.4 Special Event Trigger147FIGURE 16-2: Compare Mode Operation Block Diagram147TABLE 16-2: Registers Associated with Capture, Compare and Timer114816.5 PWM Mode149FIGURE 16-3: Simplified PWM Block Diagram149FIGURE 16-4: PWM Output14916.5.1 PWM Period149EQUATION 16-1:14916.5.2 PWM Duty Cycle149EQUATION 16-2:149EQUATION 16-3:15016.5.3 Setup for PWM Operation150TABLE 16-3: Example PWM Frequencies and Resolutions at 40 MHz150TABLE 16-4: Registers Associated with PWM and Timer215017.0 Motion Feedback Module151TABLE 17-1: Summary of Motion Feedback Module Features151FIGURE 17-1: Motion Feedback Module Block Diagram15217.1 Input Capture153FIGURE 17-2: Input Capture Block Diagram for IC1153FIGURE 17-3: Input Capture Block Diagram for IC2 and IC3154Register 17-1: CAPxCON: Input Capture x Control Register15517.1.1 Edge Capture Mode156FIGURE 17-4: Edge Capture Mode Timing15617.1.2 Period Measurement Mode15717.1.3 Pulse-Width Measurement Mode157FIGURE 17-5: Pulse-Width Measurement Mode Timing15717.1.4 Input Capture on State Change158FIGURE 17-6: Input Capture on State Change (Hall Effect Sensor Mode)15817.1.5 Entering Input Capture Mode and Capture Timing15917.1.6 Timer5 Reset15917.1.7 IC Interrupts159FIGURE 17-7: CAPx Interrupts and IC1 Special Event Trigger15917.1.8 Special Event Trigger (CAP1 Only)160TABLE 17-2: Special Event Trigger16017.1.9 Operating Modes Summary16017.1.10 Other Operating Modes160TABLE 17-3: Input Capture Time Base Reset Summary16017.2 Quadrature Encoder Interface161FIGURE 17-8: QEI Block Diagram16117.2.1 QEI Configuration162Register 17-2: QEICON: Quadrature Encoder Interface Control Register16217.2.2 QEI Modes163TABLE 17-4: QEI MOdes16317.2.3 QEI Operation163TABLE 17-5: Direction of Rotation16317.2.4 QEI Interrupts16417.2.5 QEI Sample Timing164EQUATION 17-1:164FIGURE 17-9: QEI Inputs When Sampled By the Filter (Divide Ratio = 1:1)165FIGURE 17-10: QEI Module Reset Timing on Period Match165FIGURE 17-11: QEI Module Reset Timing With the Index Input16617.2.6 Velocity Measurement167TABLE 17-6: Velocity Pulses167FIGURE 17-12: Velocity Measurement Block Diagram167FIGURE 17-13: Velocity Measurement Timing(1)16817.3 Noise Filters169Register 17-3: DFLTCON: Digital Filter Control Register169FIGURE 17-14: Noise Filter Timing Diagram (Clock Divider = 1:1)17017.4 IC and QEI Shared Interrupts170TABLE 17-7: Meaning of IC and QEI Interrupt Flags17017.5 Operation in Sleep Mode17017.5.1 3x Input Capture in Sleep Mode17017.5.2 QEI in Sleep Mode170TABLE 17-8: Registers Associated with the Motion Feedback Module17118.0 Power Control PWM Module173FIGURE 18-1: Power Control PWM Module Block Diagram174FIGURE 18-2: PWM Module Block Diagram, One Output Pair, Complementary Mode175FIGURE 18-3: PWM Module Block Diagram, One Output Pair, Independent Mode17518.1 Control Registers17618.2 Module Functionality17618.3 PWM Time Base176FIGURE 18-4: PWM Time Base Block Diagram177Register 18-1: PTCON0: PWM Timer Control Register 0178Register 18-2: PTCON1: PWM Timer Control Register 1178Register 18-3: PWMCON0: PWM Control Register 0179Register 18-4: PWMCON1: PWM Control Register 118018.3.1 Free-Running Mode18018.3.2 Single-Shot Mode18018.3.3 Continuous Up/Down Count Modes18018.3.4 PWM Time Base Prescaler180TABLE 18-1: Minimum PWM Frequency18118.3.5 PWM Time Base Postscaler18118.4 PWM Time Base Interrupts18118.4.1 Interrupts in Free-Running Mode181FIGURE 18-5: PWM Time Base Interrupt Timing, Free-Running Mode18118.4.2 Interrupts in Single-Shot Mode18218.4.3 Interrupts in Continuous Up/Down Count Mode182FIGURE 18-6: PWM Time Base Interrupt Timing, Single-Shot Mode182FIGURE 18-7: PWM Time Base Interrupt, Continuous Up/Down Count Mode18318.4.4 Interrupts in Double Update Mode184FIGURE 18-8: PWM Time Base Interrupt, Continuous Up/Down Count Mode with Double Updates18418.5 PWM Period185EQUATION 18-1: PWM Period for Free-Running Mode185EQUATION 18-2: Pwm Period for Up/Down Count Mode185EQUATION 18-3: PWM Frequency185EQUATION 18-4: PWM Resolution185TABLE 18-2: Example PWM Frequencies and Resolutions185FIGURE 18-9: PWM Period Buffer Updates in Free-Running Mode186FIGURE 18-10: PWM Period Buffer Updates in Continuous Up/Down Count Mode18618.6 PWM Duty Cycle18718.6.1 PWM Duty Cycle Registers187FIGURE 18-11: Duty Cycle Comparison18718.6.2 Duty Cycle Register Buffers18818.6.3 Edge-Aligned PWM188FIGURE 18-12: Edge-Aligned PWM188FIGURE 18-13: Duty Cycle Update Times in Continuous Up/Down Count Mode188FIGURE 18-14: Duty Cycle Update Times in Continuous Up/Down Count Mode with Double Updates18918.6.4 Center-Aligned PWM189FIGURE 18-15: Start of Center-Aligned PWM18918.6.5 Complementary PWM Operation190FIGURE 18-16: Typical Load for Complementary PWM Outputs19018.7 Dead-Time Generators19118.7.1 Dead-Time Insertion191FIGURE 18-17: Dead-Time Control Unit Block Diagram for One PWM Output Pair191FIGURE 18-18: Dead-Time Insertion for Complementary PWM191Register 18-5: DTCON: Dead-Time Control Register19218.7.2 Dead-Time Ranges19218.7.3 Decrementing the Dead-Time Counter192TABLE 18-3: Example Dead-Time Ranges19318.7.4 Dead-Time Distortion19318.8 Independent PWM Output19318.8.1 Duty Cycle Assignment in the Independent PWM Mode19318.8.2 PWM Channel Override194FIGURE 18-19: CENTER CONNECTED LOAD19418.9 Single-Pulse PWM Operation19418.10 PWM Output Override19418.10.1 Complementary Output Mode19418.10.2 Override Synchronization194FIGURE 18-20: PWM Override Bits in Complementary Mode19518.10.3 Output Override Examples196Register 18-6: OVDCOND: Output Override Control Register196Register 18-7: OVDCONS: Output State Register(1,2)196FIGURE 18-21: PWM Output Override Example #1197TABLE 18-4: PWM Output Override Example #1197TABLE 18-5: PWM Output Override Example #2197FIGURE 18-22: PWM Output Override Example #219718.11 PWM Output and Polarity Control19818.11.1 Output Pin Control19818.11.2 Output Polarity Control198FIGURE 18-23: PWM I/O Pin Block Diagram19818.11.3 PWM Output Pin Reset States19918.12 PWM Fault Inputs19918.12.1 Fault Pin Enable Bits19918.12.2 Mfault Input Modes19918.12.3 PWM Outputs While in Fault Condition20018.12.4 PWM Outputs in Debug Mode200Register 18-8: FLTCONFIG: Fault Configuration Register20118.13 PWM Update Lockout20218.14 PWM Special Event Trigger20218.14.1 Special Event Trigger Enable20218.14.2 Special Event Trigger Postscaler202TABLE 18-6: Registers Associated with the Power Control PWM Module20319.0 Synchronous Serial Port (SSP) Module20519.1 SSP Module Overview20519.2 SPI Mode205Register 19-1: SSPSTAT: Synchronous Serial Port Status Register206Register 19-2: SSPCON: Synchronous Serial Port Control Register207FIGURE 19-1: SSP Block Diagram (SPI Mode)209FIGURE 19-2: SPI Mode Timing, Master Mode210FIGURE 19-3: SPI Mode Timing (Slave Mode with CKE = 0)210FIGURE 19-4: SPI Mode Timing (Slave Mode with CKE = 1)211TABLE 19-1: Registers Associated with SPI Operation21119.3 SSP I2 C Operation212FIGURE 19-5: SSP Block Diagram (I2C™ Mode)21219.3.1 Slave Mode212TABLE 19-2: Data Transfer Received Byte Actions213FIGURE 19-6: I2C™ Waveforms for Reception (7-bit Address)214FIGURE 19-7: I2C™ Waveforms for Transmission (7-bit Address)21519.3.2 Master Mode21619.3.3 Multi-Master Mode216TABLE 19-3: Registers Associated with I2C™ Operation21620.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)21720.1 Asynchronous Operation in Power-Managed Modes217Register 20-1: TXSTA: Transmit Status And Control Register218Register 20-2: RCSTA: Receive Status And Control Register219Register 20-3: BAUDCON: Baud Rate Control Register22020.2 EUSART Baud Rate Generator (BRG)22120.2.1 Power-Managed Mode Operation22120.2.2 Sampling221TABLE 20-1: Baud Rate Formulas221EXAMPLE 20-1: Calculating Baud Rate Error222TABLE 20-2: Registers Associated with Baud Rate Generator222TABLE 20-3: Baud Rates for Asynchronous Modes22220.2.3 Auto-Baud Rate Detect225TABLE 20-4: BRG Counter Clock Rates225FIGURE 20-1: Automatic Baud Rate Calculation(1)22520.3 EUSART Asynchronous Mode22620.3.1 EUSART Asynchronous Transmitter226FIGURE 20-2: EUSART Transmit Block Diagram227FIGURE 20-3: Asynchronous Transmission227FIGURE 20-4: Asynchronous Transmission (Back to Back)227TABLE 20-5: Registers Associated with Asynchronous Transmission22820.3.2 EUSART Asynchronous Receiver22920.3.3 Setting Up 9-bit Mode with Address Detect229FIGURE 20-5: EUSART Receive Block Diagram229FIGURE 20-6: Asynchronous Reception230TABLE 20-6: Registers Associated with Asynchronous Reception23020.3.4 Auto-Wake-up on Sync Break Character231FIGURE 20-7: Auto-Wake-up Bit (WUE) Timings During Normal Operation231FIGURE 20-8: Auto-Wake-up Bit (WUE) Timings During Sleep23120.3.5 Break Character Sequence23220.3.6 Receiving a Break Character232FIGURE 20-9: Send Break Character Sequence23220.4 EUSART Synchronous Master Mode23320.4.1 EUSART Synchronous Master Transmission233FIGURE 20-10: Synchronous Transmission233FIGURE 20-11: Synchronous Transmission (Through TXEN)234TABLE 20-7: Registers Associated with Synchronous Master Transmission23420.4.2 EUSART Synchronous Master Reception235FIGURE 20-12: Synchronous Reception (Master Mode, SREN)235TABLE 20-8: Registers Associated with Synchronous Master Reception23620.5 EUSART Synchronous Slave Mode23720.5.1 EUSART Synchronous Slave Transmit237TABLE 20-9: Registers Associated with Synchronous Slave Transmission23720.5.2 EUSART Synchronous Slave Reception238TABLE 20-10: Registers Associated with Synchronous Slave Reception23821.0 10-Bit High-Speed Analog-to-Digital Converter (A/D) Module239Register 21-1: ADCON0: A/D Control Register 0240Register 21-2: ADCON1: A/D Control Register 1241Register 21-3: ADCON2: A/D Control Register 2242Register 21-4: ADCON3: A/D Control Register 3243Register 21-5: ADCHS: A/D Channel Select Register244Register 21-6: ANSEL0: Analog Select Register 0(1)245Register 21-7: ANSEL1: Analog Select Register 1(1)245FIGURE 21-1: A/D Block Diagram24621.1 Configuring the A/D Converter24721.1.1 Conversion Type24721.1.2 Conversion Mode247TABLE 21-1: Auto-Conversion Sequence Configurations24721.1.3 Conversion Sequencing24821.1.4 Triggering A/D Conversions24821.1.5 A/D Module Initialization Steps24821.2 A/D Result Buffer24921.3 A/D Acquisition Requirements249EQUATION 21-1: Acquisition Time249EQUATION 21-2: Minimum A/D Holding Capacitor Charging Time249EXAMPLE 21-1: Calculating the Minimum Required Acquisition Time250FIGURE 21-2: Analog Input Model25021.4 A/D Voltage References25121.5 Selecting and Configuring Automatic Acquisition Time25121.6 Selecting the A/D Conversion Clock251TABLE 21-2: Tad vs. Device Operating Frequencies25121.7 Operation in Power-Managed Modes25221.8 Configuring Analog Port Pins25221.9 A/D Conversions253FIGURE 21-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)253FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<3:0> = 0010, Tacq = 4 Tad)25321.9.1 A/D Result Register254FIGURE 21-5: A/D Result Justification254EQUATION 21-3: Conversion Time for Multi-Channel Modes254TABLE 21-3: Summary of A/D Registers25522.0 Low-Voltage Detect (LVD)257Register 22-1: LVDCON: Low-Voltage Detect Control Register257FIGURE 22-1: LVD Module Block Diagram (with External Input)25822.1 Operation25922.2 LVD Setup25922.3 Current Consumption25922.4 LVD Start-up Time260FIGURE 22-2: Low-Voltage Detect Waveforms26022.5 Operation During Sleep26122.6 Effects of a Reset26122.7 Applications261FIGURE 22-3: Typical Low-Voltage Detect Application261TABLE 22-1: Registers Associated with Low-Voltage Detect Module26123.0 Special Features of the CPU26323.1 Configuration Bits263TABLE 23-1: Configuration Bits and Device IDs264Register 23-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)264Register 23-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)265Register 23-3: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)266Register 23-4: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)267Register 23-5: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)268Register 23-6: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)269Register 23-7: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)270Register 23-8: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)270Register 23-9: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)271Register 23-10: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)271Register 23-11: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)272Register 23-12: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)272Register 23-13: DEVID1: Device ID Register 1 for PIC18F2331/2431/4331/4431 Devices273Register 23-14: DEVID2: Device ID Register 2 for PIC18F2331/2431/4331/4431 Devices27323.2 Watchdog Timer (WDT)27423.2.1 Control Register274FIGURE 23-1: WDT Block Diagram274Register 23-15: WDTCON: Watchdog Timer Control Register275TABLE 23-2: Summary of Watchdog Timer Registers27523.3 Two-Speed Start-up27623.3.1 Special Considerations for Using Two-Speed Start-up276FIGURE 23-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)27623.4 Fail-Safe Clock Monitor277FIGURE 23-3: FSCM Block Diagram27723.4.1 FSCM and the Watchdog Timer27723.4.2 Exiting Fail-Safe Operation277FIGURE 23-4: FSCM Timing Diagram27823.4.3 FSCM Interrupts in Power-Managed Modes27823.4.4 POR or Wake From Sleep27823.5 Program Verification and Code Protection279FIGURE 23-5: Code-Protected Program Memory for PIC18F2331/2431/4331/4431279TABLE 23-3: Summary of Code Protection Registers27923.5.1 Program Memory Code Protection280FIGURE 23-6: Table Write (WRTn) Disallowed280FIGURE 23-7: External Block Table Read (EBTRn) Disallowed281FIGURE 23-8: External Block Table Read (EBTRn) Allowed28123.5.2 Data EEPROM Code Protection28223.5.3 Configuration Register Protection28223.6 ID Locations28223.7 In-Circuit Serial Programming28223.8 In-Circuit Debugger282TABLE 23-4: Debugger Resources28223.9 Single-Supply ICSP™ Programming28224.0 Instruction Set Summary28324.1 Read-Modify-Write Operations283TABLE 24-1: Opcode Field Descriptions284FIGURE 24-1: General Format for Instructions285TABLE 24-2: PIC18FXXXX Instruction Set28624.2 Instruction Set28925.0 Development Support32525.1 MPLAB Integrated Development Environment Software32525.2 MPLAB C Compilers for Various Device Families32625.3 HI-TECH C for Various Device Families32625.4 MPASM Assembler32625.5 MPLINK Object Linker/ MPLIB Object Librarian32625.6 MPLAB Assembler, Linker and Librarian for Various Device Families32625.7 MPLAB SIM Software Simulator32725.8 MPLAB REAL ICE In-Circuit Emulator System32725.9 MPLAB ICD 3 In-Circuit Debugger System32725.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express32725.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express32825.12 MPLAB PM3 Device Programmer32825.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits32826.0 Electrical Characteristics329Absolute Maximum Ratings(†)329FIGURE 26-1: PIC18F2331/2431/4331/4431 Voltage-Frequency Graph (Industrial)330FIGURE 26-2: PIC18LF2331/2431/4331/4431 Voltage-Frequency Graph (Industrial)33026.1 DC Characteristics: Supply Voltage PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial)33126.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial)33226.3 DC Characteristics: PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial)339TABLE 26-1: Memory Programming Requirements341FIGURE 26-3: Low-Voltage Detect Characteristics342TABLE 26-2: Low-Voltage Detect Characteristics34226.4 AC (Timing) Characteristics34426.4.1 Timing Parameter Symbology34426.4.2 Timing Conditions345TABLE 26-3: Temperature and Voltage Specifications – AC345FIGURE 26-4: Load Conditions for Device Timing Specifications34526.4.3 Timing Diagrams and Specifications346FIGURE 26-5: External Clock Timing (All Modes Except PLL)346TABLE 26-4: External Clock Timing Requirements346TABLE 26-5: PLL Clock Timing Specifications (Vdd = 4.2V to 5.5V)347TABLE 26-6: Internal RC Accuracy347FIGURE 26-6: CLKO and I/O Timing348TABLE 26-7: CLKO and I/O Timing Requirements348FIGURE 26-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing349FIGURE 26-8: Brown-out Reset Timing349TABLE 26-8: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements350FIGURE 26-9: Timer0 and Timer1 External Clock Timings351TABLE 26-9: Timer0 and Timer1 External Clock Requirements351FIGURE 26-10: Capture/Compare/PWM Timings (All CCP Modules)352TABLE 26-10: Capture/Compare/PWM Requirements (All CCP Modules)352FIGURE 26-11: Example SPI Master Mode Timing (CKE = 0)353TABLE 26-11: Example SPI Mode Requirements (Master Mode, CKE = 0)353FIGURE 26-12: Example SPI Master Mode Timing (CKE = 1)354TABLE 26-12: Example SPI Mode Requirements (Master Mode, CKE = 1)354FIGURE 26-13: Example SPI Slave Mode Timing (CKE = 0)355TABLE 26-13: Example SPI Mode Requirements (Slave Mode, CKE = 0)355FIGURE 26-14: Example SPI Slave Mode Timing (CKE = 1)356TABLE 26-14: Example SPI Slave Mode Requirements (CKE = 1)356FIGURE 26-15: I2C™ Bus Start/Stop Bits Timing357TABLE 26-15: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)357FIGURE 26-16: I2C™ Bus Data Timing357TABLE 26-16: I2C™ Bus Data Requirements (Slave Mode)358TABLE 26-17: SSP I2C™ Bus Data Requirements359FIGURE 26-17: EUSART Synchronous Transmission (Master/Slave) Timing360TABLE 26-18: EUSART Synchronous Transmission Requirements360FIGURE 26-18: EUSART Synchronous Receive (Master/Slave) Timing360TABLE 26-19: EUSART Synchronous Receive Requirements360TABLE 26-20: A/D Converter Characteristics36127.0 Packaging Information36327.1 Package Marking Information36327.1 Package Marking Information (Continued)36427.2 Package Details365Appendix A: Revision History375Revision A (June 2003)375Revision B (December 2003)375Revision C (June 2007)375Revision D (September 2010)375Appendix B: Device Differences375TABLE B-1: Device Differences375Appendix C: Conversion Considerations376Appendix D: Migration from Baseline to Enhanced Devices376Appendix E: Migration From Mid-Range to Enhanced Devices377Appendix F: Migration From High-End to Enhanced Devices377INDEX379The Microchip Web Site389Customer Change Notification Service389Customer Support389Reader Response390Product Identification System391Worldwide Sales and Service392サイズ： 3.05MBページ数： 392Language: Englishマニュアルを開く
