データシート目次1.0 Electrical Characteristics62.0 Typical Performance Curves8FIGURE 2-1: Input Quiescent Current vs. Input Voltage.8FIGURE 2-2: Input Quiescent Current vs. Input Voltage.8FIGURE 2-3: Error Amplifier Frequency Response.8FIGURE 2-4: Error Amplifier Input Bias Current vs. Input Voltage.8FIGURE 2-5: Error Amplifier Sink Current vs. Input Voltage.8FIGURE 2-6: Error Amplifier Source Current vs. Input Voltage.8FIGURE 2-7: VEXT Rise Time vs. Input Voltage.9FIGURE 2-8: VEXT Fall Time vs. Input Voltage.9FIGURE 2-9: Current Sense to VEXT Delay vs. Input Voltage (MCP1630).9FIGURE 2-10: Current Sense Clamp Voltage vs. Input Voltage (MCP1630).9FIGURE 2-11: Undervoltage Lockout vs. Temperature.9FIGURE 2-12: EXT Output N-channel RDSON vs. Input Voltage.9FIGURE 2-13: EXT Output P-channel RDSON vs. Input Voltage.10FIGURE 2-14: Error Amplifier Input Offset Voltage vs. Input Voltage.10FIGURE 2-15: Error Amplifier Input Offset Voltage vs. Input Voltage.10FIGURE 2-16: Current Sense Common Mode Input Voltage Range vs. Input Voltage (MCP1630V).10FIGURE 2-17: Current Sense to VEXT Delay vs. Input Voltage (MCP1630V).103.0 MCP1630 Pin Descriptions11TABLE 3-1: pin function table113.1 Error Amplifier Output Pin (COMP)113.2 Error Amplifier Inverting Input (FB)113.3 Current Sensing Input (CS)113.4 Oscillator Input (OSC)113.5 Ground (GND)113.6 External Driver Output Pin (VEXT)113.7 Input Bias Pin (VIN)113.8 Reference Voltage Input (VREF)114.0 Detailed Description124.1 Device Overview124.2 PWM124.3 Normal Cycle by Cycle Control124.4 Error Amp/Comparator Current Limit Function124.5 0% Duty Cycle Operation124.6 Undervoltage Lockout (UVLO)134.7 Overtemperature Protection13FIGURE 4-1: Cycle-by-Cycle Timing Diagram (MCP1630).14FIGURE 4-2: Cycle-by-Cycle Timing Diagram (MCP1630V).155.0 Application Circuits/Issues165.1 Typical Applications165.2 NiMH Battery Charger Application165.3 Bidirectional Power Converter165.4 Multiple Output Converters166.0 Packaging Information176.1 Package Marking Information17Corporate Office26Atlanta26Boston26Chicago26Cleveland26Fax: 216-447-064326Dallas26Detroit26Indianapolis26Toronto26Fax: 852-2401-343126Australia - Sydney26China - Beijing26China - Shanghai26India - Bangalore26Korea - Daegu26Korea - Seoul26Singapore26Taiwan - Taipei26Fax: 43-7242-2244-39326Denmark - Copenhagen26France - Paris26Germany - Munich26Italy - Milan26Spain - Madrid26UK - Wokingham26Worldwide Sales and Service26サイズ： 345KBページ数： 26Language: Englishマニュアルを開く
ユーザーズマニュアル目次Preface5Introduction5Document Layout5Conventions Used in this Guide6Recommended Reading6The Microchip Web Site7Customer Support7Document Revision History7Chapter 1. Product Overview91.1 Introduction91.2 What is the MCP1630 Automotive Input Boost Converter Demo Board?101.3 What the MCP1630 Automotive Input Boost Converter Demo Board kit Includes10Chapter 2. Installation and Operation112.1 Introduction112.2 Features112.3 Getting Started12Appendix A. Schematic and Layouts15A.1 Introduction15A.2 Board – Schematic16A.3 Board – Top Silk Layer17A.4 Board – Top Metal Layer18A.5 Board – Bottom Metal Layer19Appendix B. Bill Of Materials (BOM)21Appendix C. Demo Board Firmware23C.1 Device Firmware23Worldwide Sales and Service24サイズ： 695KBページ数： 24Language: Englishマニュアルを開く
データシート目次TABLE 1: 8-Pin Summary48-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology31.0 Device Overview7FIGURE 1-1: PIC12F683 Block Diagram7TABLE 1-1: PIC12F683 Pinout Description82.0 Memory Organization92.1 Program Memory Organization9FIGURE 2-1: Program Memory Map and Stack for the PIC12F68392.2 Data Memory Organization92.2.1 General Purpose Register File102.2.2 Special Function Registers10FIGURE 2-2: Data Memory Map of the PIC12F68310TABLE 2-1: PIC12F683 Special Registers Summary Bank 011TABLE 2-2: PIC12F683 Special Function Registers Summary Bank 112Register 2-1: STATUS: STATUS Register13Register 2-2: OPTION_REG: OPTION Register14Register 2-3: INTCON: Interrupt Control Register15Register 2-4: PIE1: Peripheral Interrupt Enable Register 116Register 2-5: PIR1: Peripheral Interrupt Request Register 117Register 2-6: PCON: Power Control Register182.3 PCL and PCLATH19FIGURE 2-3: Loading of PC in Different Situations192.3.1 Computed GOTO192.3.2 Stack192.4 Indirect Addressing, INDF and FSR Registers19EXAMPLE 2-1: Indirect Addressing19FIGURE 2-4: Direct/Indirect Addressing PIC12F683203.0 Oscillator Module (With Fail-Safe Clock Monitor)213.1 Overview21FIGURE 3-1: PIC® MCU Clock Source Block Diagram213.2 Oscillator Control22Register 3-1: OSCCON: Oscillator Control Register223.3 Clock Source Modes233.4 External Clock Modes233.4.1 Oscillator Start-up Timer (OST)23TABLE 3-1: Oscillator Delay Examples233.4.2 EC Mode23FIGURE 3-2: External Clock (EC) Mode Operation233.4.3 LP, XT, HS Modes24FIGURE 3-3: Quartz Crystal Operation (LP, XT or HS Mode)24FIGURE 3-4: Ceramic Resonator Operation (XT or HS Mode)243.4.4 External RC Modes25FIGURE 3-5: External RC Modes253.5 Internal Clock Modes253.5.1 INTOSC and INTOSCIO Modes253.5.2 HFINTOSC25Register 3-2: OSCTUNE: Oscillator Tuning ReGister263.5.3 LFINTOSC273.5.4 Frequency Select Bits (IRCF)273.5.5 HF and LF INTOSC Clock Switch Timing27FIGURE 3-6: Internal Oscillator Switch Timing283.6 Clock Switching293.6.1 System Clock Select (SCS) Bit293.6.2 Oscillator Start-up Time-out Status (OSTS) Bit293.7 Two-Speed Clock Start-up Mode293.7.1 Two-Speed Start-up Mode Configuration293.7.2 Two-Speed Start-up Sequence293.7.3 Checking Two-Speed Clock Status30FIGURE 3-7: Two-Speed Start-up303.8 Fail-Safe Clock Monitor31FIGURE 3-8: FSCM Block Diagram313.8.1 Fail-Safe Detection313.8.2 Fail-Safe Operation313.8.3 Fail-Safe Condition Clearing313.8.4 Reset or Wake-up from Sleep31FIGURE 3-9: FSCM Timing Diagram32TABLE 3-2: Summary of Registers Associated with Clock Sources324.0 GPIO Port334.1 GPIO and the TRISIO Registers33EXAMPLE 4-1: Initializing GPIO33Register 4-1: GPIO: General Purpose I/O Register33Register 4-2: TRISIO GPIO Tri-State Register344.2 Additional Pin Functions344.2.1 ANSEL Register344.2.2 Weak Pull-ups344.2.3 Interrupt-on-Change34Register 4-3: ANSEL: Analog Select Register35Register 4-4: WPU: Weak Pull-Up Register36Register 4-5: IOC: Interrupt-on-change GPIO Register364.2.4 Ultra Low-Power Wake-up37EXAMPLE 4-2: Ultra Low-Power Wake-up Initialization374.2.5 Pin Descriptions and Diagrams38FIGURE 4-1: Block Diagram of GP038FIGURE 4-2: Block Diagram of GP139FIGURE 4-3: Block Diagram of GP239FIGURE 4-4: Block Diagram of GP340FIGURE 4-5: Block Diagram of GP440FIGURE 4-6: Block Diagram of GP541TABLE 4-1: Summary of Registers Associated with GPIO415.0 Timer0 Module435.1 Timer0 Operation435.1.1 8-bit Timer mode435.1.2 8-Bit Counter Mode43FIGURE 5-1: Block Diagram of the Timer0/WDT Prescaler435.1.3 Software Programmable Prescaler44EXAMPLE 5-1: Changing Prescaler (Timer0ÆWDT)44EXAMPLE 5-2: Changing Prescaler (WDTÆTIMER0)445.1.4 Timer0 Interrupt445.1.5 Using Timer0 with an External Clock44Register 5-1: OPTION_REG: OPTION Register45TABLE 5-1: Summary of Registers Associated with Timer0456.0 Timer1 Module with Gate Control466.1 Timer1 Operation466.2 Clock Source Selection46FIGURE 6-1: Timer1 Block Diagram466.2.1 iNternal Clock Source476.2.2 External Clock Source476.3 Timer1 Prescaler476.4 Timer1 Oscillator476.5 Timer1 Operation in Asynchronous Counter Mode476.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode476.6 Timer1 Gate476.7 Timer1 Interrupt486.8 Timer1 Operation During Sleep486.9 CCP Special Event Trigger486.10 Comparator Synchronization48FIGURE 6-2: Timer1 Incrementing Edge486.11 Timer1 Control Register49Register 6-1: T1CON: Timer1 Control Register49TABLE 6-1: Summary of Registers Associated with Timer1507.0 Timer2 Module517.1 Timer2 Operation51FIGURE 7-1: Timer2 Block Diagram51Register 7-1: T2CON: Timer 2 Control Register52TABLE 7-1: Summary of Associated Timer2 Registers528.0 Comparator Module538.1 Comparator Overview53FIGURE 8-1: Single Comparator53FIGURE 8-2: Comparator Output Block Diagram538.2 Analog Input Connection Considerations54FIGURE 8-3: Analog Input Model548.3 Comparator Configuration55FIGURE 8-4: Comparator I/O Operating Modes558.4 Comparator Control568.4.1 Comparator Output State568.4.2 Comparator Output Polarity56TABLE 8-1: Output State vs. Input Conditions568.4.3 Comparator Input Switch568.5 Comparator Response Time568.6 Comparator Interrupt Operation57FIGURE 8-5: Comparator Interrupt Timing W/O CMCON0 Read57FIGURE 8-6: Comparator Interrupt Timing With CMCON0 Read578.7 Operation During Sleep588.8 Effects of a Reset58Register 8-1: CMCON0: Comparator Configuration Register588.9 Comparator Gating Timer1598.10 Synchronizing Comparator Output to Timer159Register 8-2: CMCON1: cOMPARATOR CONFIGURATION Register598.11 Comparator Voltage Reference608.11.1 Independent Operation608.11.2 Output Voltage Selection60EQUATION 8-1: CVref Output Voltage608.11.3 Output Clamped to Vss608.11.4 Output Ratiometric to Vdd60Register 8-3: VRCON: Voltage Reference Control register60FIGURE 8-7: Comparator Voltage Reference Block Diagram61TABLE 8-2: Summary of Registers Associated with the Comparator and Voltage Reference Modules619.0 Analog-to-Digital Converter (ADC) Module63FIGURE 9-1: ADC Block Diagram639.1 ADC Configuration639.1.1 GPIO Configuration639.1.2 Channel Selection639.1.3 ADC Voltage Reference649.1.4 Conversion Clock64TABLE 9-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies (Vdd > 3.0V)64FIGURE 9-2: Analog-to-Digital Conversion Tad Cycles649.1.5 Interrupts659.1.6 Result Formatting65FIGURE 9-3: 10-Bit A/D Conversion Result Format659.2 ADC Operation659.2.1 Starting a Conversion659.2.2 Completion of a Conversion659.2.3 Terminating a conversion659.2.4 ADC Operation During Sleep669.2.5 Special Event Trigger669.2.6 A/D Conversion Procedure66EXAMPLE 9-1: A/D Conversion669.2.7 ADC Register Definitions66Register 9-1: ADCON0: A/D Control Register 067Register 9-2: ADRESH: ADC Result Register High (ADRESH) ADFM = 068Register 9-3: ADRESL: ADC Result Register Low (ADRESL) ADFM = 068Register 9-4: ADRESH: ADC Result Register High (ADRESH) ADFM = 168Register 9-5: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1689.3 A/D Acquisition Requirements69EQUATION 9-1: Acquisition Time Example69FIGURE 9-4: Analog Input Model70FIGURE 9-5: ADC Transfer Function70TABLE 9-2: Summary of Associated ADC Registers7110.0 Data EEPROM Memory73Register 10-1: EEDAT: EEPROM Data Register73Register 10-2: EEADR: EEPROM Address Register7310.1 EECON1 and EECON2 Registers74Register 10-3: EECON1: EEPROM Control Register7410.2 Reading the EEPROM Data Memory75EXAMPLE 10-1: DATA EEPROM READ7510.3 Writing to the EEPROM Data Memory75EXAMPLE 10-2: DATA EEPROM WRITE7510.4 Write Verify75EXAMPLE 10-3: WRITE VERIFY7510.4.1 Using the Data EEPROM7510.5 Protection Against Spurious Write7610.6 Data EEPROM Operation During Code-Protect76TABLE 10-1: Summary of Associated Data EEPROM Registers7611.0 Capture/Compare/PWM (CCP) Module77TABLE 11-1: CCP Mode – Timer Resources Required77Register 11-1: CCP1CON: CCP1 Control Register7711.1 Capture Mode7811.1.1 CCP1 pin Configuration78FIGURE 11-1: Capture Mode Operation Block Diagram7811.1.2 Timer1 Mode Selection7811.1.3 Software Interrupt7811.1.4 CCP Prescaler78EXAMPLE 11-1: Changing Between Capture Prescalers7811.2 Compare Mode79FIGURE 11-2: Compare Mode Operation Block Diagram7911.2.1 CCP1 Pin Configuration7911.2.2 timer1 Mode Selection7911.2.3 Software Interrupt Mode7911.2.4 Special Event Trigger7911.3 PWM Mode80FIGURE 11-3: Simplified PWM Block Diagram80FIGURE 11-4: CCP PWM Output8011.3.1 PWM period81EQUATION 11-1: PWM Period8111.3.2 PWM Duty Cycle81EQUATION 11-2: Pulse Width81EQUATION 11-3: Duty Cycle Ratio8111.3.3 PWM Resolution81EQUATION 11-4: PWM Resolution81TABLE 11-2: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)81TABLE 11-3: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)8111.3.4 Operation in Sleep Mode8211.3.5 Changes in System Clock Frequency8211.3.6 Effects of Reset8211.3.7 Setup for PWM Operation82TABLE 11-4: Registers Associated with Capture, cOMPARE and Timer183TABLE 11-5: Registers Associated with PWM and Timer28312.0 Special Features of the CPU8512.1 Configuration Bits85Register 12-1: CONFIG: Configuration Word Register8612.2 Calibration Bits8712.3 Reset87FIGURE 12-1: Simplified Block Diagram of On-Chip Reset Circuit8712.3.1 Power-on Reset8812.3.2 MCLR88FIGURE 12-2: Recommended MCLR Circuit8812.3.3 Power-up Timer (PWRT)8812.3.4 Brown-Out Reset (BOR)8912.3.5 BOR Calibration89FIGURE 12-3: Brown-out Situations8912.3.6 Time-out Sequence9012.3.7 Power Control (PCON) Register90TABLE 12-1: Time-out in Various Situations90TABLE 12-2: Status/PCON Bits and Their Significance90TABLE 12-3: Summary of Registers Associated with Brown-out Reset90FIGURE 12-4: Time-out Sequence on Power-up (Delayed MCLR)91FIGURE 12-5: Time-out Sequence on Power-up (Delayed MCLR)91FIGURE 12-6: Time-out Sequence on Power-up (MCLR with Vdd)91TABLE 12-4: Initialization Condition for Registers92TABLE 12-5: Initialization Condition for Special Registers9312.4 Interrupts9412.4.1 GP2/INT Interrupt9412.4.2 Timer0 Interrupt9512.4.3 GPIO Interrupt95FIGURE 12-7: Interrupt Logic95FIGURE 12-8: INT Pin Interrupt Timing96TABLE 12-6: Summary of Registers Associated with Interrupts9612.5 Context Saving During Interrupts97EXAMPLE 12-1: Saving Status and W Registers in RAM9712.6 Watchdog Timer (WDT)9812.6.1 WDT Oscillator9812.6.2 WDT Control98FIGURE 12-9: Watchdog Timer Block Diagram98TABLE 12-7: WDT Status98Register 12-2: WDTCON: Watchdog Timer Control Register99TABLE 12-8: Summary of Registers Associated with Watchdog Timer9912.7 Power-Down Mode (Sleep)10012.7.1 Wake-up from Sleep10012.7.2 Wake-up Using Interrupts100FIGURE 12-10: Wake-up From Sleep Through Interrupt10112.8 Code Protection10112.9 ID Locations10112.10 In-Circuit Serial Programming™102FIGURE 12-11: Typical In-Circuit Serial Programming Connection10212.11 In-Circuit Debugger102TABLE 12-9: Debugger Resources102FIGURE 12-12: 14-Pin ICD Pinout10213.0 Instruction Set Summary10313.1 Read-Modify-Write Operations103TABLE 13-1: Opcode Field Descriptions103FIGURE 13-1: General Format for Instructions103TABLE 13-2: PIC12F683 Instruction Set10413.2 Instruction Descriptions10514.0 Development Support11314.1 MPLAB Integrated Development Environment Software11314.2 MPASM Assembler11414.3 MPLAB C18 and MPLAB C30 C Compilers11414.4 MPLINK Object Linker/ MPLIB Object Librarian11414.5 MPLAB ASM30 Assembler, Linker and Librarian11414.6 MPLAB SIM Software Simulator11414.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator11514.8 MPLAB REAL ICE In-Circuit Emulator System11514.9 MPLAB ICD 2 In-Circuit Debugger11514.10 MPLAB PM3 Device Programmer11514.11 PICSTART Plus Development Programmer11614.12 PICkit 2 Development Programmer11614.13 Demonstration, Development and Evaluation Boards11615.0 Electrical Specifications117FIGURE 15-1: PIC12F683 Voltage-Frequency Graph, -40 C £ ta £ +125 C118FIGURE 15-2: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature11815.1 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended)11915.2 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended)12015.3 DC Characteristics: PIC12F683-I (Industrial)12115.4 DC Characteristics: PIC12F683-E (Extended)12215.5 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended)12315.6 Thermal Considerations12515.7 Timing Parameter Symbology126FIGURE 15-3: Load Conditions12615.8 AC Characteristics: PIC12F683 (Industrial, Extended)127FIGURE 15-4: Clock Timing127TABLE 15-1: Clock Oscillator Timing Requirements127TABLE 15-2: Oscillator Parameters128FIGURE 15-5: CLKOUT and I/O Timing129TABLE 15-3: CLKOUT and I/O Timing Parameters129FIGURE 15-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing130FIGURE 15-7: Brown-out Reset Timing and Characteristics130TABLE 15-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset ...131FIGURE 15-8: Timer0 and Timer1 External Clock Timings132TABLE 15-5: Timer0 and Timer1 External Clock Requirements132FIGURE 15-9: Capture/Compare/PWM Timings (ECCP)133TABLE 15-6: Capture/Compare/PWM Requirements (ECCP)133TABLE 15-7: Comparator Specifications134TABLE 15-8: Comparator Voltage Reference (CVref) Specifications134TABLE 15-9: PIC12F683 A/D Converter (ADC) Characteristics135TABLE 15-10: PIC12F683 A/D Conversion Requirements136FIGURE 15-10: PIC12F683 A/D Conversion Timing (Normal Mode)137FIGURE 15-11: PIC12F683 A/D Conversion Timing (Sleep Mode)13716.0 DC and AC Characteristics Graphs and Tables139FIGURE 16-1: Typical Idd vs. Fosc Over Vdd (EC Mode)139FIGURE 16-2: Maximum Idd vs. Fosc Over Vdd (EC Mode)140FIGURE 16-3: Typical Idd vs. Fosc Over Vdd (HS Mode)140FIGURE 16-4: Maximum Idd vs. Fosc Over Vdd (HS Mode)141FIGURE 16-5: Typical Idd vs. Vdd Over Fosc (XT Mode)141FIGURE 16-6: Maximum Idd vs. Vdd Over Fosc (XT Mode)142FIGURE 16-7: Typical Idd vs. Vdd Over Fosc (EXTRC Mode)142FIGURE 16-8: Maximum Idd vs. Vdd (EXTRC Mode)143FIGURE 16-9: Idd vs. Vdd Over Fosc (LFINTOSC Mode, 31 kHz)143FIGURE 16-10: Idd vs. Vdd (LP Mode)144FIGURE 16-11: Typical Idd vs. Fosc Over Vdd (HFINTOSC Mode)144FIGURE 16-12: Maximum Idd vs. Fosc Over Vdd (HFINTOSC Mode)145FIGURE 16-13: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)145FIGURE 16-14: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)146FIGURE 16-15: Comparator Ipd vs. Vdd (Both Comparators Enabled)146FIGURE 16-16: BOR Ipd VS. Vdd Over Temperature147FIGURE 16-17: Typical WDT Ipd VS. Vdd Over Temperature147FIGURE 16-18: Maximum WDT Ipd VS. Vdd Over Temperature148FIGURE 16-19: WDT Period VS. Vdd Over Temperature148FIGURE 16-20: WDT Period VS. Temperature Over Vdd (5.0V)149FIGURE 16-21: CVref Ipd VS. Vdd Over Temperature (High Range)149FIGURE 16-22: CVref Ipd VS. Vdd Over Temperature (Low Range)150FIGURE 16-23: Vol VS. Iol Over Temperature (Vdd = 3.0V)150FIGURE 16-24: Vol VS. Iol Over Temperature (Vdd = 5.0V)151FIGURE 16-25: Voh VS. Ioh Over Temperature (Vdd = 3.0V)151FIGURE 16-26: Voh VS. Ioh Over Temperature (Vdd = 5.0V)152FIGURE 16-27: TTL Input Threshold Vin VS. Vdd Over Temperature152FIGURE 16-28: Schmitt Trigger Input Threshold Vin VS. Vdd Over Temperature153FIGURE 16-29: T1OSC Ipd vs. Vdd Over Temperature (32 kHz)153FIGURE 16-30: Comparator Response Time (Rising Edge)154FIGURE 16-31: Comparator Response Time (Falling Edge)154FIGURE 16-32: LFINTOSC Frequency vs. Vdd Over Temperature (31 kHz)155FIGURE 16-33: ADC Clock Period vs. Vdd Over Temperature155FIGURE 16-34: Typical HFINTOSC Start-Up Times vs. Vdd Over Temperature156FIGURE 16-35: Maximum HFINTOSC Start-Up Times vs. Vdd Over Temperature156FIGURE 16-36: Minimum HFINTOSC Start-Up Times vs. Vdd Over Temperature157FIGURE 16-37: Typical HFINTOSC Frequency Change vs. Vdd (25 C)157FIGURE 16-38: Typical HFINTOSC Frequency Change Over Device Vdd (85 C)158FIGURE 16-39: Typical HFINTOSC Frequency Change vs. Vdd (125 C)158FIGURE 16-40: Typical HFINTOSC Frequency Change vs. Vdd (-40 C)15917.0 Packaging Information16117.1 Package Marking Information16117.2 Package Details162Appendix A: Data Sheet Revision History167Appendix B: Migrating From Other PIC® Devices167INDEX169The Microchip Web Site173Customer Change Notification Service173Customer Support173Reader Response174Product Identification System175Worldwide Sales and Service176サイズ： 2.92MBページ数： 176Language: Englishマニュアルを開く
