ユーザーズマニュアル目次0000. . . 0 1 0 0 . . . . . . . . . . . 0 0 0001000SECTION 1.1 INTRODUCTION3SECTION 1.2 ORIGIN OF DIGITAL SIGNAL PROCESSING3SECTION 2.1 DSP56K CENTRAL ARCHITECTURE OVERVIEW3SECTION 2.2 DATA BUSES3SECTION 3.1 DATA ARITHMETIC LOGIC UNIT3SECTION 3.2 OVERVIEW AND DATA ALU ARCHITECTURE3SECTION 4.2 AGU ARCHITECTURE34.2.1 Address Register Files (Rn)3SECTION 5.1 PROGRAM CONTROL UNIT3SECTION 5.2 OVERVIEW3SECTION 6.1 INSTRUCTION SET INTRODUCTION3SECTION 6.2 SYNTAX3SECTION 6.3 INSTRUCTION FORMATS3SECTION 7.1 PROCESSING STATES3SECTION 7.2 NORMAL PROCESSING STATE37.2.1 Instruction Pipeline3SECTION 8.1 PORT A OVERVIEW3SECTION 8.2 PORT A INTERFACE3SECTION 9.1 PLL CLOCK OSCILLATOR INTRODUCTION3SECTION 9.2 PLL COMPONENTS3SECTION 10.1 INTRODUCTION3SECTION 10.2 ON-CHIP EMULATION (OnCE) PINS3SECTION 11.1 USER SUPPORT3SECTION A.1 APPENDIX A INTRODUCTION3SECTION A.2 INSTRUCTION GUIDE3SECTION B.1 INTRODUCTION3SECTION B.2 BENCHMARK PROGRAMS3SECTION 2.3 ADDRESS BUSES44.2.2 Offset Register Files (Nn)49.2.1 Phase Detector and Charge Pump Loop Filter4SECTION 11.2 MOTOROLA DSP PRODUCT SUPPORT411.2.1 DSP56000CLASx Assembler/Simulator411.2.2 Macro Cross Assembler Features:4SECTION A.3 NOTATION4SECTION 2.4 DATA ALU5SECTION 2.5 ADDRESS GENERATION UNIT5SECTION 2.6 PROGRAM CONTROL UNIT53.2.1 Data ALU Input Registers (X1, X0, Y1, Y0)54.2.3 Modifier Register Files (Mn)54.2.4 Address ALU5SECTION 5.3 PROGRAM CONTROL UNIT (PCU) ARCHITECTURE55.3.1 Program Decode Controller55.3.2 Program Address Generator (PAG)56.3.1 Operand Sizes58.2.1 Read/Write Control Signals58.2.1.1 Program Memory Select (PS)58.2.1.2 Data Memory Select (DS)58.2.1.3 X/Y Select (X/Y)58.2.2 Port A Address and Data Bus Signals59.2.2 Voltage Controlled Oscillator (VCO)59.2.3 Frequency Multiplier59.2.4 Low Power Divider (LPD)59.2.5 PLL Control Register (PCTL)59.2.5.1 PCTL Multiplication Factor Bits (MF0-MF11) - Bits 0-11511.2.3 Simulator Features:511.2.4 DSP56KCCx Language Compiler Features:5SECTION 2.7 MEMORY EXPANSION PORT (PORT A)6SECTION 2.8 ON-CHIP EMULATOR (OnCE)6SECTION 2.9 PHASE-LOCKED LOOP (PLL) BASED CLOCKING63.2.2 MAC and Logic Unit64.2.5 Address Output Multiplexers6SECTION 4.3 PROGRAMMING MODEL65.3.3 Program Interrupt Controller65.3.4 Instruction Pipeline Format66.3.2 Data Organization in Registers66.3.2.1 Data ALU Registers68.2.2.1 Address (A0–A15)68.2.2.2 Data (D0–D23)68.2.3 Port A Bus Control Signals68.2.3.1 Read Enable (RD)68.2.3.2 Write Enable (WR)68.2.3.3 Port A Access Control Signals68.2.4 Interrupt and Mode Control68.2.5 Port A Wait States69.2.5.2 PCTL Division Factor Bits (DF0-DF3) - Bits 12-156SECTION 10.3 OnCE CONTROLLER AND SERIAL INTERFACE6SECTION 11.3 DSP56KADSx APPLICATION DEVELOPMENT SYSTEM6System Hardware Features:6System Software Features:63.2.3 Data ALU A and B Accumulators74.3.1 Address Register Files (R0 - R3 and R4 - R7)74.3.2 Offset Register Files (N0 - N3 and N4 - N7)76.3.2.2 AGU Registers79.2.5.3 PCTL XTAL Disable Bit (XTLD) - Bit 1679.2.5.4 PCTL STOP Processing State Bit (PSTP) - Bit 177SECTION 11.4 Dr. BuB ELECTRONIC BULLETIN BOARD74.3.3 Modifier Register Files (M0 - M3 and M4 - M7)8SECTION 4.4 ADDRESSING8SECTION 5.4 PROGRAMMING MODEL85.4.1 Program Counter86.3.2.3 Program Control Registers87.2.2 Summary of Pipeline-Related Restrictions89.2.5.5 PCTL PLL Enable Bit (PEN) - Bit 188SECTION 1.2 SUMMARY OF DSP56K FAMILY FEATURES93.2.4 Accumulator Shifter93.2.5 Data Shifter/Limiter93.2.5.1 Limiting (Saturation Arithmetic)94.4.1 Address Register Indirect Modes94.4.1.1 No Update94.4.1.2 Postincrement By 194.4.1.3 Postdecrement By 195.4.2 Status Register96.3.3 Data Organization in Memory99.2.5.7 PCTL Chip Clock Source Bit (CSRC) - Bit 2199.2.5.8 PCTL CKOUT Clock Source Bit (CKOS) - Bit 2299.2.5.9 PCTL Reserved Bit - Bit 239SECTION 9.3 PLL PINS93.2.5.2 Scaling10SECTION 3.3 DATA REPRESENTATION AND ROUNDING104.4.1.4 Postincrement By Offset Nn105.4.2.1 Carry (Bit 0)105.4.2.2 Overflow (Bit 1)105.4.2.3 Zero (Bit 2)105.4.2.4 Negative (Bit 3)105.4.2.5 Unnormalized (Bit 4)10SECTION 7.3 EXCEPTION PROCESSING STATE10SECTION A.4 ADDRESSING MODES10SECTION 1.3 MANUAL ORGANIZATION11011114.4.1.5 Postdecrement By Offset Nn115.4.2.6 Extension (Bit 5)115.4.2.7 Limit (Bit 6)115.4.2.8 Scaling Bit (Bit 7)116.3.4 Operand References116.3.4.1 Program References116.3.4.2 Stack References116.3.4.3 Register References116.3.4.4 Memory References116.3.4.4.1 X Memory References11SECTION 9.4 PLL OPERATION CONSIDERATIONS119.4.1 Operating Frequency119.4.2 Hardware Reset11SECTION 10.4 OnCE MEMORY BREAKPOINT LOGIC114.4.1.6 Indexed By Offset Nn125.4.2.9 Interrupt Masks (Bits 8 and 9)125.4.2.10 Scaling Mode (Bits 10 and 11)126.3.4.4.2 Y Memory References126.3.4.4.3 L Memory References126.3.4.4.4 YX Memory References126.3.5 Addressing Modes127.3.1 Interrupt Types127.3.2 Interrupt Priority Structure129.4.3 Operation with PLL Disabled129.4.4 Changing the MF0-MF11 Bits124.4.1.7 Predecrement By 1135.4.2.11 Reserved Status (Bit 12)135.4.2.12 Trace Mode (Bit 13)135.4.2.13 Double Precision Multiply Mode (Bit 14)135.4.2.14 Loop Flag (Bit 15)136.3.5.1 Register Direct Modes136.3.5.1.1 Data or Control Register Direct136.3.5.1.2 Address Register Direct136.3.5.2 Address Register Indirect Modes139.4.5 Change of DF0-DF3 Bits139.4.6 Loss of Lock139.4.7 STOP Processing State13SECTION 10.5 OnCE TRACE LOGIC13A.4.1 Addressing Mode Modifiers134.4.2 Address Modifier Arithmetic Types145.4.3 Operating Mode Register145.4.4 System Stack146.3.5.3 Special Addressing Modes146.3.5.3.1 Immediate Data146.3.5.3.2 Absolute Address146.3.5.3.3 Immediate Short146.3.5.3.4 Short Jump Address146.3.5.3.5 Absolute Short147.3.2.1 Interrupt Priority Levels149.4.8 CKOUT Considerations149.4.9 Synchronization Among EXTAL, CKOUT, and the Internal Clock14SECTION 10.6 METHODS OF ENTERING THE DEBUG MODE14SECTION A.5 CONDITION CODE COMPUTATION145.4.5 Stack Pointer Register157.3.2.2 Exception Priorities Within an IPL15SECTION A.6 PARALLEL MOVE DESCRIPTIONS15SECTION 3.4 DOUBLE PRECISION MULTIPLY MODE164.4.2.1 Linear Modifier (Mn=$FFFF)165.4.5.1 Stack Pointer (Bits 0–3)165.4.5.2 Stack Error Flag (Bit 4)165.4.5.3 Underflow Flag (Bit 5)166.3.5.3.6 I/O Short166.3.5.3.7 Implicit Reference167.3.3 Interrupt Sources167.3.3.1 Hardware Interrupt Sources16BUS REGISTER16SECTION 11.5 MOTOROLA DSP NEWS16SECTION 11.6 MOTOROLA FIELD APPLICATION ENGINEERS16SECTION 11.7 DESIGN HOTLINE– 1-800-521-627416SECTION 11.8 DSP HELP LINE – (512) 891-323016SECTION 11.9 MARKETING INFORMATION– (512) 891-203016SECTION 11.11 UNIVERSITY SUPPORT – (512) 891-3098165.4.5.4 Reserved Stack Pointer Registration (Bits 6–23)175.4.6 Loop Address Register175.4.7 Loop Counter Register175.4.8 Programming Model Summary177.3.3.2 Software Interrupt Sources17SECTION 11.13 REFERENCE BOOKS AND MANUALS17SECTION A.7 INSTRUCTION DESCRIPTIONS174.4.2.2 Modulo Modifier18SECTION 10.8 PROGRAM ADDRESS BUS HISTORY BUFFER18SECTION 3.5 DATA ALU PROGRAMMING MODEL19SECTION 3.6 DATA ALU SUMMARY19SECTION 10.9 SERIAL PROTOCOL DESCRIPTION19REQUIREMENTS196.3.5.4 Addressing Modes Summary20SECTION 6.4 INSTRUCTION GROUPS20SECTION 10.11 USING THE OnCE204.4.2.3 Reverse-Carry Modifier (Mn=$0000)226.4.1 Arithmetic Instructions227.3.3.3 Other Interrupt Sources226.4.2 Logical Instructions236.4.3 Bit Manipulation Instructions246.4.4 Loop Instructions247.3.4 Interrupt Arbitration247.3.5 Interrupt Instruction Fetch244.4.2.4 Address-Modifier-Type Encoding Summary257.3.6 Instructions Preceding the Interrupt Instruction Fetch256.4.5 Move Instructions267.3.7 Interrupt Instruction Execution266.4.6 Program Control Instructions27SECTION 7.4 RESET PROCESSING STATE33SECTION 7.5 WAIT PROCESSING STATE36SECTION 7.6 STOP PROCESSING STATE37SECTION A.8 INSTRUCTION TIMING224SECTION A.9 INSTRUCTION SEQUENCE RESTRICTIONS235A.9.1 Restrictions Near the End of DO Loops236A.9.2 Other DO Restrictions237A.9.3 ENDDO Restrictions237A.9.4 RTI and RTS Restrictions238A.9.5 SP and SSH/SSL Manipulation Restrictions238A.9.6 R, N, and M Register Restrictions240A.9.7 Fast Interrupt Routines240A.9.8 REP Restrictions241SECTION A.10 INSTRUCTION ENCODING241A.10.1 Partial Encodings for Use in Instruction Encoding242Portion of an Instruction246Allow Parallel Moves248A.10.4 Parallel Instruction Encoding of the Operation Code2590011110010100001001011サイズ: 3.21MBページ数: 596Language: Englishマニュアルを開く