NEC PD78058F(A) マニュアル

目次

• COVER

  1
• MAJOR REVISIONS IN THIS EDITION

  6
• PREFACE

  7
• CHAPTER 1 OUTLINE (uPD78058F SUBSERIES)

  35
  • 1.1 Features

    35
  • 1.2 Applications

    36
  • 1.3 Ordering Information

    36
  • 1.4 Quality Grade

    37
  • 1.5 Pin Configuration (Top View)

    38
  • 1.6 78K/0 Series Expansion

    41
  • 1.7 Block Diagram

    43
  • 1.8 Outline of Function

    44
  • 1.9 Differences Between the uPD78058F and uPD78058F(A)

    45
  • 1.10 Mask Options

    46
• CHAPTER 2 OUTLINE (uPD78058FY SUBSERIES)

  47
  • 2.1 Features

    47
  • 2.2 Applications

    48
  • 2.3 Ordering Information

    48
  • 2.4 Quality Grade

    49
  • 2.5 Pin Configuration (Top View)

    50
  • 2.6 78K/0 Series Expansion

    53
  • 2.7 Block Diagram

    55
  • 2.8 Outline of Function

    56
  • 2.9 Differences Between the uPD78058FY and uPD78058FY(A)

    57
  • 2.10 Mask Options

    58
• CHAPTER 3 PIN FUNCTION (uPD78058F SUBSERIES)

  59
  • 3.1 Pin Function List

    59
    • 3.1.1 Normal operating mode pins

      59
    • 3.1.2 PROM programming mode pins (PROM versions only)

      64
  • 3.2 Description of Pin Functions

    65
    • 3.2.1 P00 to P07 (Port 0)

      65
    • 3.2.2 P10 to P17 (Port 1)

      66
    • 3.2.3 P20 to P27 (Port 2)

      66
    • 3.2.4 P30 to P37 (Port 3)

      67
    • 3.2.5 P40 to P47 (Port 4)

      68
    • 3.2.6 P50 to P57 (Port 5)

      68
    • 3.2.7 P60 to P67 (Port 6)

      68
    • 3.2.8 P70 to P72 (Port 7)

      69
    • 3.2.9 P120 to P127 (Port 12)

      70
    • 3.2.10 P130 and P131 (Port 13)

      70
    • 3.2.11 AVREF0

      70
    • 3.2.12 AVREF1

      70
    • 3.2.13 AVDD

      71
    • 3.2.14 AVSS

      71
    • 3.2.15 RESET#

      71
    • 3.2.16 X1 and X2

      71
    • 3.2.17 XT1 and XT2

      71
    • 3.2.18 VDD

      71
    • 3.2.19 VSS

      71
    • 3.2.20 VPP (PROM versions only)

      71
    • 3.2.21 IC (Mask ROM version only)

      72
  • 3.3 Input/output Circuits and Recommended Connection of Unused Pins

    73
• CHAPTER 4 PIN FUNCTION (uPD78058FY SUBSERIES)

  77
  • 4.1 Pin Function List

    77
    • 4.1.1 Normal operating mode pins

      77
    • 4.1.2 PROM programming mode pins (PROM versions only)

      82
  • 4.2 Description of Pin Functions

    83
    • 4.2.1 P00 to P07 (Port 0)

      83
    • 4.2.2 P10 to P17 (Port 1)

      84
    • 4.2.3 P20 to P27 (Port 2)

      84
    • 4.2.4 P30 to P37 (Port 3)

      85
    • 4.2.5 P40 to P47 (Port 4)

      86
    • 4.2.6 P50 to P57 (Port 5)

      86
    • 4.2.7 P60 to P67 (Port 6)

      86
    • 4.2.8 P70 to P72 (Port 7)

      87
    • 4.2.9 P120 to P127 (Port 12)

      88
    • 4.2.10 P130 and P131 (Port 13)

      88
    • 4.2.11 AVREF0

      88
    • 4.2.12 AVREF1

      88
    • 4.2.13 AVDD

      89
    • 4.2.14 AVSS

      89
    • 4.2.15 RESET#

      89
    • 4.2.16 X1 and X2

      89
    • 4.2.17 XT1 and XT2

      89
    • 4.2.18 VDD

      89
    • 4.2.19 VSS

      89
    • 4.2.20 VPP (PROM versions only)

      89
    • 4.2.21 IC (Mask ROM version only)

      90
  • 4.3 Input/output Circuits and Recommended Connection of Unused Pins

    91
• CHAPTER 5 CPU ARCHITECTURE

  95
  • 5.1 Memory Spaces

    95
    • 5.1.1 Internal program memory space

      98
    • 5.1.2 Internal data memory space

      99
    • 5.1.3 Special Function Register (SFR) area

      99
    • 5.1.4 External memory space

      99
    • 5.1.5 Data memory addressing

      100
  • 5.2 Processor Registers

    103
    • 5.2.1 Control registers

      103
    • 5.2.2 General registers

      106
    • 5.2.3 Special Function Register (SFR)

      108
  • 5.3 Instruction Address Addressing

    112
    • 5.3.1 Relative addressing

      112
    • 5.3.2 Immediate addressing

      113
    • 5.3.3 Table indirect addressing

      114
    • 5.3.4 Register addressing

      115
  • 5.4 Operand Address Addressing

    116
    • 5.4.1 Implied addressing

      116
    • 5.4.2 Register addressing

      117
    • 5.4.3 Direct addressing

      118
    • 5.4.4 Short direct addressing

      119
    • 5.4.5 Special-Function Register (SFR) addressing

      121
    • 5.4.6 Register indirect addressing

      122
    • 5.4.7 Based addressing

      123
    • 5.4.8 Based indexed addressing

      124
    • 5.4.9 Stack addressing

      124
• CHAPTER 6 PORT FUNCTIONS

  125
  • 6.1 Port Functions

    125
  • 6.2 Port Configuration

    130
    • 6.2.1 Port 0

      130
    • 6.2.2 Port 1

      132
    • 6.2.3 Port 2 (uPD78058F Subseries)

      133
    • 6.2.4 Port 2 (uPD78058FY Subseries)

      135
    • 6.2.5 Port 3

      137
    • 6.2.6 Port 4

      138
    • 6.2.7 Port 5

      139
    • 6.2.8 Port 6

      140
    • 6.2.9 Port 7

      142
    • 6.2.10 Port 12

      144
    • 6.2.11 Port 13

      145
  • 6.3 Port Function Control Registers

    146
  • 6.4 Port Function Operations

    152
    • 6.4.1 Writing to input/output port

      152
    • 6.4.2 Reading from input/output port

      152
    • 6.4.3 Operations on input/output port

      153
  • 6.5 Selection of Mask Option

    153
• CHAPTER 7 CLOCK GENERATOR

  155
  • 7.1 Clock Generator Functions

    155
  • 7.2 Clock Generator Configuration

    155
  • 7.3 Clock Generator Control Register

    157
  • 7.4 System Clock Oscillator

    161
    • 7.4.1 Main system clock oscillator

      161
    • 7.4.2 Subsystem clock oscillator

      162
    • 7.4.3 Scaler

      164
    • 7.4.4 When no subsystem clocks are used

      164
  • 7.5 Clock Generator Operations

    165
    • 7.5.1 Main system clock operations

      166
    • 7.5.2 Subsystem clock operations

      167
  • 7.6 Changing System Clock and CPU Clock Settings

    167
    • 7.6.1 Time required for switchover between system clock and CPU clock

      167
    • 7.6.2 System clock and CPU clock switching procedure

      169
• CHAPTER 8 16-BIT TIMER/EVENT COUNTER

  171
  • 8.1 Overview of the uPD78058F and 78058FY Subseries On-Chip Timers

    171
  • 8.2 16-Bit Timer/Event Counter Functions

    173
  • 8.3 16-Bit Timer/Event Counter Configuration

    174
  • 8.4 16-Bit Timer/Event Counter Control Registers

    178
  • 8.5 16-Bit Timer/Event Counter Operations

    187
    • 8.5.1 Interval timer operations

      187
    • 8.5.2 PWM output operations

      189
    • 8.5.3 PPG output operations

      192
    • 8.5.4 Pulse width measurement operations

      193
    • 8.5.5 External event counter operation

      200
    • 8.5.6 Square-wave output operation

      202
    • 8.5.7 One-shot pulse output operation

      204
  • 8.6 16-Bit Timer/Event Counter Operating Precautions

    208
• CHAPTER 9 8-BIT TIMER/EVENT COUNTERS

  211
  • 9.1 8-Bit Timer/Event Counter Function

    211
    • 9.1.1 8-bit timer/event counter mode

      211
    • 9.1.2 16-bit timer/event counter mode

      214
  • 9.2 8-Bit Timer/Event Counter Configuration

    216
  • 9.3 8-Bit Timer/Event Counter Control Registers

    220
  • 9.4 8-Bit Timer/Event Counter Operation

    225
    • 9.4.1 8-bit timer/event counter mode

      225
    • 9.4.2 16-bit timer/event counter mode

      230
  • 9.5 Cautions on 8-Bit Timer/Event Counters

    236
• CHAPTER 10 WATCH TIMER

  239
  • 10.1 Watch Timer Functions

    239
  • 10.2 Watch Timer Configuration

    240
  • 10.3 Watch Timer Control Registers

    240
  • 10.4 Watch Timer Operations

    244
    • 10.4.1 Watch timer operation

      244
    • 10.4.2 Interval timer operation

      244
• CHAPTER 11 WATCHDOG TIMER

  245
  • 11.1 Watchdog Timer Functions

    245
  • 11.2 Watchdog Timer Configuration

    247
  • 11.3 Watchdog Timer Control Registers

    248
  • 11.4 Watchdog Timer Operations

    251
    • 11.4.1 Watchdog timer operation

      251
    • 11.4.2 Interval timer operation

      252
• CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT

  253
  • 12.1 Clock Output Control Circuit Functions

    253
  • 12.2 Clock Output Control Circuit Configuration

    254
  • 12.3 Clock Output Function Control Registers

    254
• CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT

  257
  • 13.1 Buzzer Output Control Circuit Functions

    257
  • 13.2 Buzzer Output Control Circuit Configuration

    257
  • 13.3 Buzzer Output Function Control Registers

    258
• CHAPTER 14 A/D CONVERTER

  261
  • 14.1 A/D Converter Functions

    261
  • 14.2 A/D Converter Configuration

    262
  • 14.3 A/D Converter Control Registers

    265
  • 14.4 A/D Converter Operations

    269
    • 14.4.1 Basic operations of A/D converter

      269
    • 14.4.2 Input voltage and conversion results

      271
    • 14.4.3 A/D converter operating mode

      272
  • 14.5 A/D Converter Cautions

    274
• CHAPTER 15 D/A CONVERTER

  279
  • 15.1 D/A Converter Functions

    279
  • 15.2 D/A Converter Configuration

    280
  • 15.3 D/A Converter Control Registers

    282
  • 15.4 Operations of D/A Converter

    283
  • 15.5 Cautions Related to D/A Converter

    284
• CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (uPD78058F SUBSERIES)

  285
  • 16.1 Serial Interface Channel 0 Functions

    286
  • 16.2 Serial Interface Channel 0 Configuration

    288
  • 16.3 Serial Interface Channel 0 Control Registers

    292
  • 16.4 Serial Interface Channel 0 Operations

    299
    • 16.4.1 Operation stop mode

      299
    • 16.4.2 3-wire serial I/O mode operation

      300
    • 16.4.3 SBI mode operation

      305
    • 16.4.4 2-wire serial I/O mode operation

      331
    • 16.4.5 SCK0#/P27 pin output manipulation

      336
• CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (uPD78058FY SUBSERIES)

  337
  • 17.1 Serial Interface Channel 0 Functions

    338
  • 17.2 Serial Interface Channel 0 Configuration

    340
  • 17.3 Serial Interface Channel 0 Control Registers

    345
  • 17.4 Serial Interface Channel 0 Operations

    353
    • 17.4.1 Operation stop mode

      353
    • 17.4.2 3-wire serial I/O mode operation

      354
    • 17.4.3 2-wire serial I/O mode operation

      358
    • 17.4.4 I2C bus mode operation

      363
    • 17.4.5 Cautions on use of I2C bus mode

      380
    • 17.4.6 Restrictions in I2C bus mode

      383
    • 17.4.7 SCK0#/SCL/P27 pin output manipulation

      385
• CHAPTER 18 SERIAL INTERFACE CHANNEL 1

  387
  • 18.1 Serial Interface Channel 1 Functions

    387
  • 18.2 Serial Interface Channel 1 Configuration

    388
  • 18.3 Serial Interface Channel 1 Control Registers

    391
  • 18.4 Serial Interface Channel 1 Operations

    399
    • 18.4.1 Operation stop mode

      399
    • 18.4.2 3-wire serial I/O mode operation

      400
    • 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function

      403
• CHAPTER 19 SERIAL INTERFACE CHANNEL 2

  433
  • 19.1 Serial Interface Channel 2 Functions

    433
  • 19.2 Serial Interface Channel 2 Configuration

    434
  • 19.3 Serial Interface Channel 2 Control Registers

    438
  • 19.4 Serial Interface Channel 2 Operation

    446
    • 19.4.1 Operation stop mode

      446
    • 19.4.2 Asynchronous serial interface (UART) mode

      448
    • 19.4.3 3-wire serial I/O mode

      461
    • 19.4.4 Restrictions on using UART mode

      468
• CHAPTER 20 REAL-TIME OUTPUT PORT

  471
  • 20.1 Real-Time Output Port Functions

    471
  • 20.2 Real-Time Output Port Configuration

    472
  • 20.3 Real-Time Output Port Control Registers

    474
• CHAPTER 21 INTERRUPT AND TEST FUNCTIONS

  477
  • 21.1 Interrupt Function Types

    477
  • 21.2 Interrupt Sources and Configuration

    478
  • 21.3 Interrupt Function Control Registers

    482
  • 21.4 Interrupt Servicing Operations

    491
    • 21.4.1 Non-maskable interrupt acknowledge operation

      491
    • 21.4.2 Maskable Interrupt request reception

      494
    • 21.4.3 Software interrupt request acknowledge operation

      497
    • 21.4.4 Multiple interrupt servicing

      497
    • 21.4.5 Interrupt request reserve

      501
  • 21.5 Test Functions

    502
    • 21.5.1 Registers controlling the test function

      502
    • 21.5.2 Test input signal acknowledge operation

      504
• CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION

  505
  • 22.1 External Device Expansion Functions

    505
  • 22.2 External Device Expansion Function Control Register

    508
  • 22.3 External Device Expansion Function Timing

    510
• CHAPTER 23 STANDBY FUNCTION

  515
  • 23.1 Standby Function and Configuration

    515
    • 23.1.1 Standby function

      515
    • 23.1.2 Standby function control register

      516
  • 23.2 Standby Function Operations

    517
    • 23.2.1 HALT mode

      517
    • 23.2.2 STOP mode

      520
• CHAPTER 24 RESET FUNCTION

  523
  • 24.1 Reset Function

    523
• CHAPTER 25 ROM CORRECTION

  527
  • 25.1 ROM Correction Functions

    527
  • 25.2 ROM Correction Configuration

    527
  • 25.3 ROM Correction Control Registers

    529
  • 25.4 ROM Correction Application

    530
  • 25.5 ROM Correction Example

    533
  • 25.6 Program Execution Flow

    534
  • 25.7 Cautions on ROM Correction

    536
• CHAPTER 26 uPD78P058F, 78P058FY

  537
  • 26.1 Memory Size Switching Register

    538
  • 26.2 Internal Expansion RAM Size Switching Register

    539
  • 26.3 PROM Programming

    540
    • 26.3.1 Operating modes

      540
    • 26.3.2 PROM write procedure

      542
    • 26.3.3 PROM read procedure

      546
  • 26.4 Screening of One-Time PROM Versions

    547
• CHAPTER 27 INSTRUCTION SET

  549
  • 27.1 Legends Used in Operation List

    550
    • 27.1.1 Operand identifiers and description methods

      550
    • 27.1.2 Description of "operation" column

      551
    • 27.1.3 Description of "flag" column

      551
  • 27.2 Operation List

    552
  • 27.3 Instructions Listed by Addressing Type

    560
• APPENDIX A. DIFFERENCES AMONG uPD78054, 78058F, AND 780058 SUBSERIES

  565
• APPENDIX B DEVELOPMENT TOOLS

  567
  • B.1 Language Processing Software

    570
  • B.2 PROM Programming Tool

    571
    • B.2.1 Hardware

      571
    • B.2.2 Software

      571
  • B.3 Debugging Tool

    572
    • B.3.1 Hardware

      572
    • B.3.2 Software

      574
  • B.4 OS for IBM PC

    576
  • B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A

    576
• APPENDIX C EMBEDDED SOFTWARE

  581
  • C.1 Real-time OS

    582
• APPENDIX D REGISTER INDEX

  585
  • D.1 Register Index

    585
• APPENDIX E REVISION HISTORY

  591