Omron C200HE マニュアル

目次

• Front

  1
• C200HX/C200HG/C200HE Programmable Controllers Operation Manual

  2
• Notice:

  3
• TABLE OF CONTENTS

  4
• About this Manual:

  7
• PRECAUTIONS

  8
  • 1 Intended Audience

    9
  • 2 General Precautions

    9
  • 3 Safety Precautions

    9
  • 4 Operating Environment Precautions

    10
  • 5 Application Precautions

    10
  • 6 Conformance to EC Directives

    12
• SECTION 1 Introduction

  13
  • 1-1 Overview

    14
  • 1-2 The Origins of PC Logic

    14
  • 1-3 PC Terminology

    15
  • 1-4 OMRON Product Terminology

    16
  • 1-5 Overview of PC Operation

    16
  • 1-6 Peripheral Devices

    17
  • 1-7 Available Manuals

    18
  • 1-8 C200HX/HG/HE Features

    19
    • 1-8-1 C200HS and C200HX/HG/HE Capabilities

      19
    • 1-8-2 Program Compatibility

      20
• SECTION 2 Hardware Considerations

  23
  • 2-1 CPU Unit Components

    24
    • 2-1-1 CPU Unit Indicators

      25
    • 2-1-2 Peripheral Device Connection

      25
  • 2-2 PC Configuration

    27
  • 2-3 CPU Unit Capabilities

    27
  • 2-4 Memory Cassettes

    28
    • 2-4-1 Hardware and Software Settings

      29
    • 2-4-2 Writing/Reading UM Data

      29
    • 2-4-3 Writing/Reading IOM Data

      30
  • 2-5 CPU Unit DIP Switch

    32
  • 2-6 Operating without a Backup Battery

    33
• SECTION 3 Memory Areas

  35
  • 3-1 Introduction

    36
    • 3-1-1 Data Area Overview

      36
    • 3-1-2 IR/SR Area Overview

      37
  • 3-2 Data Area Structure

    37
  • 3-3 IR (Internal Relay) Area

    41
  • 3-4 SR (Special Relay) Area

    45
    • 3-4-1 SYSMAC NET/SYSMAC LINK System

      50
    • 3-4-2 Remote I/O Systems

      51
    • 3-4-3 Link System Flags and Control Bits

      52
    • 3-4-4 Forced Status Hold Bit

      53
    • 3-4-5 I/O Status Hold Bit

      54
    • 3-4-6 Output OFF Bit

      54
    • 3-4-7 FAL (Failure Alarm) Area

      54
    • 3-4-8 Low Battery Flag

      54
    • 3-4-9 Cycle Time Error Flag

      55
    • 3-4-10 I/O Verification Error Flag

      55
    • 3-4-11 First Cycle Flag

      55
    • 3-4-12 Clock Pulse Bits

      55
    • 3-4-13 Step Flag

      56
    • 3-4-14 Group-2 Error Flag

      56
    • 3-4-15 Special Unit Error Flag

      56
    • 3-4-16 Instruction Execution Error Flag, ER

      56
    • 3-4-17 Arithmetic Flags

      56
    • 3-4-18 Interrupt Subroutine Areas

      57
    • 3-4-19 RS-232C Port Communications Areas

      57
    • 3-4-20 Peripheral Port Communications Areas

      58
    • 3-4-21 Memory Cassette Areas

      58
    • 3-4-22 Data Transfer Error Bits

      59
    • 3-4-23 Ladder Diagram Memory Areas

      59
    • 3-4-24 Memory Error Flags

      59
    • 3-4-25 Data Save Flags

      60
    • 3-4-26 Transfer Error Flags

      60
    • 3-4-27 PC Setup Error Flags

      60
    • 3-4-28 Clock and Keyboard Mapping

      60
    • 3-4-29 Group-2 Error Flags

      60
    • 3-4-30 Special I/O Unit Restart Bits and Error Flags

      60
  • 3-5 AR (Auxiliary Relay) Area

    60
    • 3-5-1 Restarting Special I/O Units

      62
    • 3-5-2 Slave Rack Error Flags

      63
    • 3-5-3 Group-2 Error Flags

      63
    • 3-5-4 Optical I/O Unit and I/O Terminal Error Flags

      63
    • 3-5-5 SYSMAC LINK System Data Link Settings

      64
    • 3-5-6 Error History Bits

      64
    • 3-5-7 Active Node Flags

      64
    • 3-5-8 SYSMAC LINK/SYSMAC NET Link System Service Time

      65
    • 3-5-9 Calendar/Clock Area and Bits

      65
    • 3-5-10 TERMINAL Mode Key Bits

      66
    • 3-5-11 Power OFF Counter

      66
    • 3-5-12 SYSMAC LINK – Peripheral Device Flags

      66
    • 3-5-13 Cycle Time Flag

      67
    • 3-5-14 Link Unit Mounted Flags

      67
    • 3-5-15 CPU Unit-mounting Device Mounted Flag

      67
    • 3-5-16 FPD Trigger Bit

      67
    • 3-5-17 Data Tracing Flags and Control Bits

      67
    • 3-5-18 Cycle Time Indicators

      67
  • 3-6 DM (Data Memory) Area

    68
    • 3-6-1 Expansion DM Area

      69
    • 3-6-2 Special I/O Unit Data

      70
    • 3-6-3 Error History Area

      70
    • 3-6-4 PC Setup

      72
    • 3-6-5 Communications Board Settings

      77
    • 3-6-6 Special I/O Unit Area Settings

      79
  • 3-7 HR (Holding Relay) Area

    80
  • 3-8 TC (Timer/Counter) Area

    80
  • 3-9 LR (Link Relay) Area

    81
  • 3-10 UM Area

    82
  • 3-11 TR (Temporary Relay) Area

    83
  • 3-12 EM (Extended Data Memory) Area

    83
    • 3-12-1 Using the EM Area

      83
    • 3-12-2 The Current EM Bank

      84
• SECTION 4 Writing and Inputting the Program

  85
  • 4-1 Basic Procedure

    86
  • 4-2 Instruction Terminology

    86
  • 4-3 Program Capacity

    87
  • 4-4 Basic Ladder Diagrams

    87
    • 4-4-1 Basic Terms

      88
    • 4-4-2 Mnemonic Code

      88
    • 4-4-3 Ladder Instructions

      89
    • 4-4-4 OUTPUT and OUTPUT NOT

      92
    • 4-4-5 The END Instruction

      92
    • 4-4-6 Logic Block Instructions

      93
    • 4-4-7 Coding Multiple Right-hand Instructions

      100
  • 4-5 The Programming Console

    100
    • 4-5-1 The Keyboard

      100
    • 4-5-2 PC Modes

      103
    • 4-5-3 The Display Message Switch

      103
  • 4-6 Preparation for Operation

    103
    • 4-6-1 Entering the Password

      104
    • 4-6-2 Buzzer

      104
    • 4-6-3 Clearing Memory

      105
    • 4-6-4 Registering the I/O Table

      108
    • 4-6-5 Clearing Error Messages

      109
    • 4-6-6 Verifying the I/O Table

      109
    • 4-6-7 Reading the I/O Table

      111
    • 4-6-8 Clearing the I/O Table

      113
    • 4-6-9 SYSMAC NET Link Table Transfer

      114
  • 4-7 Inputting, Modifying, and Checking the Program

    116
    • 4-7-1 Setting and Reading from Program Memory Address

      116
    • 4-7-2 Entering and Editing Programs

      117
    • 4-7-3 Checking the Program

      120
    • 4-7-4 Displaying the Cycle Time

      122
    • 4-7-5 Program Searches

      123
    • 4-7-6 Inserting and Deleting Instructions

      124
    • 4-7-7 Branching Instruction Lines

      127
    • 4-7-8 Jumps

      131
  • 4-8 Controlling Bit Status

    132
    • 4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN

      133
    • 4-8-2 KEEP

      133
    • 4-8-3 Self-maintaining Bits (Seal)

      133
  • 4-9 Work Bits (Internal Relays)

    134
  • 4-10 Programming Precautions

    136
  • 4-11 Program Execution

    138
  • 4-12 Special I/O Unit Interface Programs

    138
    • 4-12-1 Restarting Special I/O Units

      138
    • 4-12-2 Special I/O Unit Error Processing Program

      139
    • 4-12-3 Changing the Special I/O Unit Settings

      139
    • 4-12-4 Special I/O Unit I/O Refreshing Interval

      140
    • 4-12-5 Reducing the Cycle Time

      141
  • 4-13 Analog Timer Unit Programming

    142
    • 4-13-1 Operation

      142
    • 4-13-2 Bit Allocation and DIP Switch Settings

      143
    • 4-13-3 Example Program

      144
• SECTION 5 Instruction Set

  147
  • 5-1 Notation

    150
  • 5-2 Instruction Format

    150
  • 5-3 Data Areas, Definer Values, and Flags

    150
  • 5-4 Differentiated Instructions

    152
  • 5-5 Expansion Instructions

    153
  • 5-6 Coding Right-hand Instructions

    154
  • 5-7 Instruction Set Lists

    157
    • 5-7-1 Function Codes

      157
  • 5-8 Ladder Diagram Instructions

    161
    • 5-8-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT

      161
    • 5-8-2 AND LOAD and OR LOAD

      162
  • 5-9 Bit Control Instructions

    162
    • 5-9-1 OUTPUT and OUTPUT NOT – OUT and OUT NOT

      162
    • 5-9-2 DIFFERENTIATE UP and DOWN – DIFU(13) and DIFD(14)

      163
    • 5-9-3 SET and RESET – SET and RSET

      165
    • 5-9-4 KEEP – KEEP(11)

      166
  • 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)

    167
  • 5-11 JUMP and JUMP END – JMP(04) and JME(05)

    169
  • 5-12 END – END(01)

    170
  • 5-13 NO OPERATION – NOP(00)

    170
  • 5-14 Timer and Counter Instructions

    170
    • 5-14-1 TIMER – TIM

      171
    • 5-14-2 HIGH-SPEED TIMER – TIMH(15)

      176
    • 5-14-3 TOTALIZING TIMER – TTIM(87)

      177
    • 5-14-4 COUNTER – CNT

      178
    • 5-14-5 REVERSIBLE COUNTER – CNTR(12)

      181
  • 5-15 Data Shifting

    183
    • 5-15-1 SHIFT REGISTER – SFT(10)

      183
    • 5-15-2 REVERSIBLE SHIFT REGISTER – SFTR(84)

      185
    • 5-15-3 ARITHMETIC SHIFT LEFT – ASL(25)

      187
    • 5-15-4 ARITHMETIC SHIFT RIGHT – ASR(26)

      187
    • 5-15-5 ROTATE LEFT – ROL(27)

      188
    • 5-15-6 ROTATE RIGHT – ROR(28)

      188
    • 5-15-7 ONE DIGIT SHIFT LEFT – SLD(74)

      189
    • 5-15-8 ONE DIGIT SHIFT RIGHT – SRD(75)

      189
    • 5-15-9 WORD SHIFT – WSFT(16)

      190
    • 5-15-10 ASYNCHRONOUS SHIFT REGISTER – ASFT(17)

      190
  • 5-16 Data Movement

    192
    • 5-16-1 MOVE – MOV(21)

      192
    • 5-16-2 MOVE NOT – MVN(22)

      192
    • 5-16-3 BLOCK SET – BSET(71)

      193
    • 5-16-4 BLOCK TRANSFER – XFER(70)

      194
    • 5-16-5 DATA EXCHANGE – XCHG(73)

      195
    • 5-16-6 SINGLE WORD DISTRIBUTE – DIST(80)

      195
    • 5-16-7 DATA COLLECT – COLL(81)

      197
    • 5-16-8 MOVE BIT – MOVB(82)

      199
    • 5-16-9 MOVE DIGIT – MOVD(83)

      200
    • 5-16-10 TRANSFER BITS – XFRB(62)

      201
    • 5-16-11 EM BLOCK TRANSFER – XFR2(––)

      202
    • 5-16-12 EM BANK TRANSFER – BXF2(––)

      203
  • 5-17 Data Comparison

    204
    • 5-17-1 MULTI-WORD COMPARE – MCMP(19)

      204
    • 5-17-2 COMPARE – CMP(20)

      205
    • 5-17-3 DOUBLE COMPARE – CMPL(60)

      208
    • 5-17-4 BLOCK COMPARE – BCMP(68)

      209
    • 5-17-5 TABLE COMPARE – TCMP(85)

      211
    • 5-17-6 AREA RANGE COMPARE – ZCP(88)

      212
    • 5-17-7 DOUBLE AREA RANGE COMPARE – ZCPL(––)

      213
    • 5-17-8 SIGNED BINARY COMPARE – CPS(––)

      214
    • 5-17-9 DOUBLE SIGNED BINARY COMPARE – CPSL(––)

      215
  • 5-18 Data Conversion

    216
    • 5-18-1 BCD-TO-BINARY – BIN(23)

      216
    • 5-18-2 DOUBLE BCD-TO-DOUBLE BINARY – BINL(58)

      217
    • 5-18-3 BINARY-TO-BCD – BCD(24)

      217
    • 5-18-4 DOUBLE BINARY-TO-DOUBLE BCD – BCDL(59)

      218
    • 5-18-5 HOURS-TO-SECONDS – SEC(65)

      219
    • 5-18-6 SECONDS-TO-HOURS – HMS(66)

      220
    • 5-18-7 4-TO-16/8-TO-256 DECODER – MLPX(76)

      221
    • 5-18-8 16-TO-4/256-TO-8 ENCODER – DMPX(77)

      224
    • 5-18-9 7-SEGMENT DECODER – SDEC(78)

      227
    • 5-18-10 ASCII CONVERT – ASC(86)

      230
    • 5-18-11 ASCII-TO-HEXADECIMAL – HEX(––)

      231
    • 5-18-12 SCALING – SCL(––)

      234
    • 5-18-13 COLUMN TO LINE – LINE(63)

      236
    • 5-18-14 LINE TO COLUMN – COLM(64)

      237
    • 5-18-15 2’S COMPLEMENT – NEG(––)

      238
    • 5-18-16 DOUBLE 2’S COMPLEMENT – NEGL(––)

      239
  • 5-19 BCD Calculations

    240
    • 5-19-1 INCREMENT – INC(38)

      240
    • 5-19-2 DECREMENT – DEC(39)

      240
    • 5-19-3 SET CARRY – STC(40)

      241
    • 5-19-4 CLEAR CARRY – CLC(41)

      241
    • 5-19-5 BCD ADD – ADD(30)

      241
    • 5-19-6 DOUBLE BCD ADD – ADDL(54)

      242
    • 5-19-7 BCD SUBTRACT – SUB(31)

      243
    • 5-19-8 DOUBLE BCD SUBTRACT – SUBL(55)

      245
    • 5-19-9 BCD MULTIPLY – MUL(32)

      247
    • 5-19-10 DOUBLE BCD MULTIPLY – MULL(56)

      248
    • 5-19-11 BCD DIVIDE – DIV(33)

      248
    • 5-19-12 DOUBLE BCD DIVIDE – DIVL(57)

      249
    • 5-19-13 FLOATING POINT DIVIDE – FDIV(79)

      250
    • 5-19-14 SQUARE ROOT – ROOT(72)

      253
  • 5-20 Binary Calculations

    255
    • 5-20-1 BINARY ADD – ADB(50)

      255
    • 5-20-2 BINARY SUBTRACT – SBB(51)

      257
    • 5-20-3 BINARY MULTIPLY – MLB(52)

      260
    • 5-20-4 BINARY DIVIDE – DVB(53)

      260
    • 5-20-5 DOUBLE BINARY ADD – ADBL(––)

      261
    • 5-20-6 DOUBLE BINARY SUBTRACT – SBBL(––)

      263
    • 5-20-7 SIGNED BINARY MULTIPLY – MBS(––)

      265
    • 5-20-8 DOUBLE SIGNED BINARY MULTIPLY – MBSL(––)

      266
    • 5-20-9 SIGNED BINARY DIVIDE – DBS(––)

      267
    • 5-20-10 DOUBLE SIGNED BINARY DIVIDE – DBSL(––)

      268
  • 5-21 Special Math Instructions

    269
    • 5-21-1 FIND MAXIMUM – MAX(––)

      269
    • 5-21-2 FIND MINIMUM – MIN(––)

      270
    • 5-21-3 AVERAGE VALUE – AVG(––)

      271
    • 5-21-4 SUM – SUM(––)

      273
    • 5-21-5 ARITHMETIC PROCESS – APR(69)

      275
    • 5-21-6 PID CONTROL – PID(––)

      278
  • 5-22 Logic Instructions

    287
    • 5-22-1 COMPLEMENT – COM(29)

      287
    • 5-22-2 LOGICAL AND – ANDW(34)

      288
    • 5-22-3 LOGICAL OR – ORW(35)

      289
    • 5-22-4 EXCLUSIVE OR – XORW(36)

      290
    • 5-22-5 EXCLUSIVE NOR – XNRW(37)

      291
  • 5-23 Subroutines and Interrupt Control

    291
    • 5-23-1 Subroutines

      291
    • 5-23-2 Interrupts

      292
    • 5-23-3 SUBROUTINE ENTER – SBS(91)

      295
    • 5-23-4 SUBROUTINE DEFINE and RETURN – SBN(92)/RET(93)

      296
    • 5-23-5 MACRO – MCRO(99)

      297
    • 5-23-6 INTERRUPT CONTROL – INT(89)

      299
  • 5-24 Step Instructions

    303
    • 5-24-1 STEP DEFINE and STEP START–STEP(08)/SNXT(09)

      303
  • 5-25 Special Instructions

    312
    • 5-25-1 FAILURE ALARM – FAL(06) and SEVERE FAILURE ALARM – FALS(07)

      312
    • 5-25-2 CYCLE TIME – SCAN(18)

      313
    • 5-25-3 TRACE MEMORY SAMPLING – TRSM(45)

      314
    • 5-25-4 MESSAGE DISPLAY – MSG(46)

      315
    • 5-25-5 LONG MESSAGE – LMSG(47)

      316
    • 5-25-6 TERMINAL MODE – TERM(48)

      317
    • 5-25-7 WATCHDOG TIMER REFRESH – WDT(94)

      318
    • 5-25-8 I/O REFRESH – IORF(97)

      318
    • 5-25-9 GROUP-2 HIGH-DENSITY I/O REFRESH – MPRF(61)

      319
    • 5-25-10 BIT COUNTER – BCNT(67)

      320
    • 5-25-11 FRAME CHECKSUM – FCS(––)

      320
    • 5-25-12 FAILURE POINT DETECTION – FPD(––)

      322
    • 5-25-13 DATA SEARCH – SRCH(––)

      326
    • 5-25-14 EXPANSION DM READ – XDMR(––)

      327
    • 5-25-15 INDIRECT EM ADDRESSING – IEMS(––)

      328
    • 5-25-16 SELECT EM BANK – EMBC(––)

      329
  • 5-26 Network Instructions

    330
    • 5-26-1 NETWORK SEND – SEND(90)

      330
    • 5-26-2 NETWORK RECEIVE – RECV(98)

      335
    • 5-26-3 About Network Communications

      339
  • 5-27 Serial Communications Instructions

    341
    • 5-27-1 RECEIVE – RXD(––)

      341
    • 5-27-2 TRANSMIT – TXD(––)

      343
    • 5-27-3 CHANGE RS-232C SETUP – STUP(––)

      345
    • 5-27-4 PROTOCOL MACRO – PMCR(––)

      347
  • 5-28 Advanced I/O Instructions

    348
    • 5-28-1 7-SEGMENT DISPLAY OUTPUT – 7SEG(––)

      348
    • 5-28-2 DIGITAL SWITCH INPUT – DSW(––)

      351
    • 5-28-3 HEXADECIMAL KEY INPUT – HKY(––)

      355
    • 5-28-4 TEN KEY INPUT – TKY(––)

      358
    • 5-28-5 MATRIX INPUT – MTR(––)

      360
  • 5-29 Special I/O Unit Instructions

    362
    • 5-29-1 SPECIAL I/O UNIT READ – IORD(––)

      362
    • 5-29-2 SPECIAL I/O UNIT WRITE – IOWR(––)

      363
    • 5-29-3 PCMCIA CARD MACRO – CMCR(––)

      365
• SECTION 6 Program Execution Timing

  370
  • 6-1 Cycle Time

    371
  • 6-2 Calculating Cycle Time

    375
    • 6-2-1 PC with I/O Units Only

      376
    • 6-2-2 PC with Host Link and Remote I/O Master Units

      376
  • 6-3 Instruction Execution Times

    378
  • 6-4 I/O Response Time

    387
    • 6-4-1 Basic Systems

      387
    • 6-4-2 Remote I/O Systems

      388
    • 6-4-3 Host Link Systems

      391
    • 6-4-4 PC Link Systems

      391
    • 6-4-5 One-to-one Link I/O Response Time

      394
    • 6-4-6 Interrupt Response Times

      396
• SECTION 7 Program Monitoring and Execution

  399
  • 7-1 Monitoring Operation and Modifying Data

    400
  • 7-2 Programming Console Operations

    400
  • 7-2-1 Bit/Word Monitor

    400
  • 7-2-2 Forced Set/Reset

    403
  • 7-2-3 Forced Set/Reset Cancel

    405
  • 7-2-4 Hexadecimal/BCD Data Modification

    406
  • 7-2-5 Hex/ASCII Display Change

    408
  • 7-2-6 4-digit Hex/Decimal Display Change

    409
  • 7-2-7 8-digit Hex/Decimal Display Change

    410
  • 7-2-8 Differentiation Monitor

    411
  • 7-2-9 3-word Monitor

    412
  • 7-2-10 3-word Data Modification

    412
  • 7-2-11 Binary Monitor

    413
  • 7-2-12 Binary Data Modification

    415
  • 7-2-13 Changing Timer/Counter SV

    416
  • 7-2-14 Expansion Instruction Function Code Assignments

    419
  • 7-2-15 UM Area Allocation

    420
  • 7-2-16 Reading and Setting the Clock

    421
  • 7-2-17 Expansion Keyboard Mapping

    421
  • 7-2-18 Keyboard Mapping

    422
• SECTION 8 Serial Communications

  426
  • 8-1 Introduction

    427
  • 8-2 Host Link Communications

    428
    • 8-2-1 Host Link Command Summary

      428
    • 8-2-2 Host Link Communications

      431
    • 8-2-3 Example Programs

      434
  • 8-3 RS-232C Communications

    435
    • 8-3-1 Communications Frame Structure

      436
    • 8-3-2 Communications Procedure

      436
    • 8-3-3 Application Example

      438
  • 8-4 One-to-one PC Links

    439
  • 8-5 NT Links

    441
  • 8-6 The Protocol Macro Function

    442
    • 8-6-1 Introduction

      442
    • 8-6-2 Communications Board Settings

      445
    • 8-6-3 Communications Procedure

      446
    • 8-6-4 Application Example

      449
• SECTION 9 Troubleshooting

  451
  • 9-1 Alarm Indicators

    452
  • 9-2 Programmed Alarms and Error Messages

    452
  • 9-3 Reading and Clearing Errors and Messages

    452
  • 9-4 Error Messages

    453
  • 9-5 Error Flags

    457
  • 9-6 Host Link Errors

    458
• SECTION 10 Host Link Commands

  460
  • 10-1 Host Link Command Summary

    461
  • 10-2 Host Link End Codes

    462
    • 10-2-1 End Code Summary

      462
    • 10-2-2 Command/End Code Table

      464
  • 10-3 Host Link Commands

    465
    • 10-3-1 IR/SR AREA READ –– RR

      465
    • 10-3-2 LR AREA READ –– RL

      466
    • 10-3-3 HR AREA READ –– RH

      467
    • 10-3-4 PV READ –– RC

      468
    • 10-3-5 TC STATUS READ –– RG

      469
    • 10-3-6 DM AREA READ –– RD

      470
    • 10-3-7 AR AREA READ –– RJ

      471
    • 10-3-8 EM AREA READ –– RE

      471
    • 10-3-9 IR/SR AREA WRITE –– WR

      472
    • 10-3-10 LR AREA WRITE –– WL

      473
    • 10-3-11 HR AREA WRITE –– WH

      474
    • 10-3-12 PV WRITE –– WC

      475
    • 10-3-13 TC STATUS WRITE –– WG

      476
    • 10-3-14 DM AREA WRITE –– WD

      477
    • 10-3-15 AR AREA WRITE –– WJ

      478
    • 10-3-16 EM AREA WRITE –– WE

      479
    • 10-3-17 SV READ 1 –– R#

      480
    • 10-3-18 SV READ 2 –– R$

      481
    • 10-3-19 SV READ 3 –– R%

      483
    • 10-3-20 SV CHANGE 1 –– W#

      484
    • 10-3-21 SV CHANGE 2 –– W$

      485
    • 10-3-22 SV CHANGE 3 –– W%

      487
    • 10-3-23 STATUS READ –– MS

      488
    • 10-3-24 STATUS WRITE –– SC

      490
    • 10-3-25 ERROR READ –– MF

      491
    • 10-3-26 FORCED SET –– KS

      492
    • 10-3-27 FORCED RESET –– KR

      493
    • 10-3-28 MULTIPLE FORCED SET/RESET –– FK

      495
    • 10-3-29 FORCED SET/RESET CANCEL –– KC

      496
    • 10-3-30 PC MODEL READ –– MM

      497
    • 10-3-31 TEST–– TS

      498
    • 10-3-32 PROGRAM READ –– RP

      499
    • 10-3-33 PROGRAM WRITE –– WP

      500
    • 10-3-34 I/O TABLE GENERATE –– MI

      501
    • 10-3-35 COMPOUND COMMAND –– QQMR

      502
    • 10-3-36 COMPOUND COMMAND DATA READ –– QQIR

      503
    • 10-3-37 ABORT –– XZ

      504
    • 10-3-38 INITIALIZE ––

      505
    • 10-3-39 TXD RESPONSE –– EX

      505
    • 10-3-40 Undefined Command –– IC

      506
• Appendix

  507
  • Appendix A Standard Models

    507
  • Appendix B Programming Instructions

    522
  • Appendix C Error and Arithmetic Flag Operation

    528
  • Appendix D Word Assignment Recording Sheets

    532
  • Appendix E Program Coding Sheet

    537
  • Appendix F Data Conversion Tables

    539
  • Appendix G Extended ASCII

    541
• Glossary

  542
• Index

  558
• Revision History

  564