Texas Instruments TPS59650 Evaluation Module TPS59650EVM-753 マニュアル

目次

• Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System

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  • 1 Description

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    • 1.1 Typical Applications

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    • 1.2 Features

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  • 2 TPS59650EVM-753 Power System Block Diagram

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  • 3 Electrical Performance Specifications

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  • 4 Test Setup

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    • 4.1 Test Equipment

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      • 4.1.1 PC Computer (Host Computer)

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      • 4.1.2 USB Cable

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      • 4.1.3 TPS59650 USB driver and SVID GUI Installation

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      • 4.1.4 DC Source

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      • 4.1.5 Meters

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      • 4.1.6 Load

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      • 4.1.7 Oscilloscope

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    • 4.2 Recommended Wire Gauge

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    • 4.3 Recommended Test Setup

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    • 4.4 USB Cable Connections

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    • 4.5 Input Connections

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    • 4.6 Output Connections

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  • 5 Configuration

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    • 5.1 CPU and GPU Configuration

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      • 5.1.1 CPU/GPU Current Limit Trip Selection (J10 for CPU and J12 for GPU)

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      • 5.1.2 CPU Frequency Selection (J11)

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      • 5.1.3 GPU Frequency Selection (J13)

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      • 5.1.4 F2808 DSP Program Mode Selection (J39)

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      • 5.1.5 5Vin Bias Voltage Option (J33)

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      • 5.1.6 On Board Dynamic Load Selection (S3 for CPU, S2(upper) for GPU, S2(lower) for VCCIO)

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      • 5.1.7 IMVP-7 VR_ON Enable Selection (S4)

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    • 5.2 1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration

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      • 5.2.1 VDDQ S3, S5 Enable Selection

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    • 5.3 1.05V VCCIO Configuration

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      • 5.3.1 1.05V Enable Selection (S1)

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      • 5.3.2 VCCIO Output Voltage Selection (J14)

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      • 5.3.3 On Board Dyanamic Load Enable Pin (J23)

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  • 6 Test Procedure

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    • 6.1 Line/Load Regulation and Efficiency Measurement Procedure

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      • 6.1.1 CPU

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      • 6.1.2 GPU

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      • 6.1.3 VDDQ

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      • 6.1.4 VCCIO

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    • 6.2 Equipment Shutdown

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  • 7 Performance Data and Typical Characteristic Curves

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    • 7.1 CPU 3-Phase Operation

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    • 7.2 CPU 2-Phase Operation

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    • 7.3 CPU1-Phase Operation

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    • 7.4 GPU 2 Phase Operation

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    • 7.5 GPU 1 Phase Operation

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    • 7.6 1.05V VCCIO

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    • 7.7 1.2V VDDQ

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  • 8 EVM Assembly Drawings and PCB Layout

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  • 9 Bill of Materials

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  • 10 Schematics

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• Important Notices

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