Motorola 146-174 MHz 사용자 설명서
August, 1996
6880904Z07-O
4-1
Section 4
Theory of Operation
Overview
This section provides a detailed theory of operation for the
GP350 and its components: the microcomputer, the receiver,
the transmitter, and the frequency generation circuitry.
GP350 and its components: the microcomputer, the receiver,
the transmitter, and the frequency generation circuitry.
Microcomputer
The GP350 VHF and UHF radios use the Motorola
68HC11A8 microcomputer, U401, which utilizes:
68HC11A8 microcomputer, U401, which utilizes:
• 7.9488 MHz clock rate
• Multiplexed 8-bit address/data lines
• 16-bit addressing
• Internal watchdog circuitry
• Analog to digital conversion input ports
The microcomputer’s operating program is permanently
written or “masked” within the microcomputer. Included in
U401 is an EEPROM memory which stores channel, signal-
ling, and scan list information.
written or “masked” within the microcomputer. Included in
U401 is an EEPROM memory which stores channel, signal-
ling, and scan list information.
Microcomputer Power-Up and Reset Routine
On power-up U401’s reset line (pin 43) is held low by the
AFIC (U402) until the synthesizer (U201) provides a stable
2.1 MHz output. When U402 releases its control, U401’s
hardware holds the reset line low until it verifies that clock
Y401 is operational. When the reset line goes “high,” U401’s
hardware delays briefly to allow Y401 to stabilize, then the
software begins executing port assignments, RAM checking,
and initialization. A fixed delay of 100 ms is added to allow
the audio circuitry to settle. Next, an alert beep is generated
and the steady state software begins to execute (buttons are
read, radio circuits are controlled).
AFIC (U402) until the synthesizer (U201) provides a stable
2.1 MHz output. When U402 releases its control, U401’s
hardware holds the reset line low until it verifies that clock
Y401 is operational. When the reset line goes “high,” U401’s
hardware delays briefly to allow Y401 to stabilize, then the
software begins executing port assignments, RAM checking,
and initialization. A fixed delay of 100 ms is added to allow
the audio circuitry to settle. Next, an alert beep is generated
and the steady state software begins to execute (buttons are
read, radio circuits are controlled).
U401’s reset line can be controlled directly by the 5V regu-
lator (U411), the AFIC, and the microcomputer, and indi-
rectly by the synthesizer. U411 drives the reset line low (via
pin 3) if it loses regulation. This prevents possible latch-up
or overwriting of registers in the microcomputer because the
reset line is higher in voltage than pin 55 of U401 (VDD).
lator (U411), the AFIC, and the microcomputer, and indi-
rectly by the synthesizer. U411 drives the reset line low (via
pin 3) if it loses regulation. This prevents possible latch-up
or overwriting of registers in the microcomputer because the
reset line is higher in voltage than pin 55 of U401 (VDD).
U401 can drive the reset line low if it detects a fault condition
such as an expired watchdog timer, software stuck in an infi-
nite loop, unplanned hardware inputs, static zaps, etc.
such as an expired watchdog timer, software stuck in an infi-
nite loop, unplanned hardware inputs, static zaps, etc.
The AFIC and synthesizer can control the reset line during
power-up, as outlined above.
power-up, as outlined above.
Receiver
The receiver of the GP350 UHF and VHF radios consists of
4 major blocks each: the front-end module, the double bal-
anced mixer, the 45.1 MHz IF and the back-end IF IC.
4 major blocks each: the front-end module, the double bal-
anced mixer, the 45.1 MHz IF and the back-end IF IC.
The UHF and VHF front-end modules consist of three blocks
of circuitry each: A pre-selector, RF amplifier and a post-
selector filter. These three items are located on a receiver
module pc-board that stands perpendicular to the main radio
pc-board. This module is enclosed in a shield to prevent radi-
ation into and out of the module. All filters on the UHF and
VHF modules are fixed tuned designs to eliminate the need
for factory tuning and to provide wide-band operation.
of circuitry each: A pre-selector, RF amplifier and a post-
selector filter. These three items are located on a receiver
module pc-board that stands perpendicular to the main radio
pc-board. This module is enclosed in a shield to prevent radi-
ation into and out of the module. All filters on the UHF and
VHF modules are fixed tuned designs to eliminate the need
for factory tuning and to provide wide-band operation.
The shunt and series coupled resonator topology yields a
more symmetrical frequency response to guard against
strong out of band signals that could produce IM products.
more symmetrical frequency response to guard against
strong out of band signals that could produce IM products.
The worst case image frequency in the VHF band is
90.2 MHz above the filter passband. The 3 db bandwidth is
approximately 35 MHz, centered at 160 MHz. The center of
the band insertion loss is approximately 1.9 db. The 4-pole
filter is designed to operate with a 50 ohm input termination,
while the output termination is the input impedance of the
RF amplifier that follows it.
90.2 MHz above the filter passband. The 3 db bandwidth is
approximately 35 MHz, centered at 160 MHz. The center of
the band insertion loss is approximately 1.9 db. The 4-pole
filter is designed to operate with a 50 ohm input termination,
while the output termination is the input impedance of the
RF amplifier that follows it.
The UHF pre-selector filter is a 3-pole,.01 db Chebyshev
bandpass design implemented in a shunt coupled resonator
topology. This topology maximizes the attenuation at the
worst case image frequency for this receiver, which is 90.2
MHz below the filter passband. The 3 db bandwidth is
approximately 45 MHz, centered at 454 MHz. The center of
the band insertion loss is approximately 2.2 db. The 3-pole
filter is designed to operate with a 50 ohm input termination,
while the output termination is the input impedance of the
RF amplifier that follows it.
bandpass design implemented in a shunt coupled resonator
topology. This topology maximizes the attenuation at the
worst case image frequency for this receiver, which is 90.2
MHz below the filter passband. The 3 db bandwidth is
approximately 45 MHz, centered at 454 MHz. The center of
the band insertion loss is approximately 2.2 db. The 3-pole
filter is designed to operate with a 50 ohm input termination,
while the output termination is the input impedance of the
RF amplifier that follows it.
The RF amplifier, Q1, is a Motorola MMBR571 NPN device
biased in a common emitter configuration. The amplifier is
stabilized by the shunt feedback resistor R3, and has approx-
imately 16.5 db of gain with a noise figure of about 3.0 db
(VHF) and 2.2 db (UHF). The amplifier draws 4 ma of cur-
rent and is supplied by the receiver 5 volt supply (indicated
as “+5R” on the schematics and block diagrams).
biased in a common emitter configuration. The amplifier is
stabilized by the shunt feedback resistor R3, and has approx-
imately 16.5 db of gain with a noise figure of about 3.0 db
(VHF) and 2.2 db (UHF). The amplifier draws 4 ma of cur-
rent and is supplied by the receiver 5 volt supply (indicated
as “+5R” on the schematics and block diagrams).
Terminating the RF amplifier is the post-selector filter. This
filter is a 3-pole for VHF and a 4-pole for UHF,.01 db Che-
byshev design which is also implemented in a series coupled
resonator topology for maximum image attenuation. The 3
db bandwidth is approximately 38 MHz centered at 160
MHz for VHF and 42.5 MHz centered at 454 MHz for UHF.
filter is a 3-pole for VHF and a 4-pole for UHF,.01 db Che-
byshev design which is also implemented in a series coupled
resonator topology for maximum image attenuation. The 3
db bandwidth is approximately 38 MHz centered at 160
MHz for VHF and 42.5 MHz centered at 454 MHz for UHF.