Renesas rl78 사용자 설명서
RL78/G1A
CHAPTER 21 VOLTAGE DETECTOR
Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
<R>
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2)
Lower limit of operation voltage
LVIF flag
V
LVDL
V
LVDH
V
POR
= 1.51 V (TYP.)
V
PDR
= 1.50 V (TYP.)
Supply voltage (V
DD
)
LVIMK flag
(set by software)
Operation status
INTLVI
LVIIF flag
Internal reset signal
LVD reset signal
POR reset signal
LVIRF flag
LVIOMSK flag
LVISEN flag
(set by software)
LVIMD flag
LVILV flag
When a condition of V
DD
is V
DD
< V
LVDH
after releasing the mask,
a reset is generated because of LVIMD = 1 (reset mode).
H
Note 1
Cleared by
software
software
Normal
operation
operation
RESET
Time
Cleared by software
RESET
RESET
Save
processing
Wait for stabilization by software (400
μs or 5 clocks of f
IL
)
Note 3
Cleared
Cleared by
software
software
Note 2
Cleared by
software
software
Note 3
Cleared
Normal
operation
operation
Save processing
(Notes and Remark are listed on the next page.)
R01UH0305EJ0200 Rev.2.00
767
Jul 04, 2013