Texas Instruments TMS320C6726 사용자 설명서
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2.6 High-Performance Crossbar Switch
SYSCLK3
SYSCLK1
SYSCLK2
SYSCLK3
BR3
BR4
2
1
Priority
EMIF
External
Memory
Memory
SDRAM/
Flash
Priority
2
1
3
4
T2
SYSCLK2
SYSCLK1
BR1
SYSCLK2
SYSCLK1
BR2
Program
Master
Port
(PMP)
CPU
Slave
Port
(CSP)
Data
Master
Port
(DMP)
Memory Controller
M1
T1
M2
Priority
1
2
3
PLL
SPI0
I2C0
I2C1
RTI
SPI1
Peripheral Configuration Bus
McASP2
McASP1
McASP0
McASP DMA Bus
Priority
1
2
3
Priority
1
2
T4
T3
dMAX MAX0 Unit Master Port − High Priority
dMAX MAX1 Unit Master Port − Second Priority
Memory Controller DMP − Data Read/Write by CPU
UHPI Master Interface (External Host CPU)
UHPI
Universal Host-Port
Interface
M5
MAX0
MAX1
1
2
3
Priority
Config
dMAX
T5
M3
M4
External
Host MCU
Config
ROM
RAM
CPU
Program
Cache
Crossbar
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus
masters and targets.
masters and targets.
illustrates the connectivity of the crossbar switch.
Figure 2-4. Block Diagram of Crossbar Switch
As shown in
, there are five bus masters:
M1
Memory controller DMP for CPU data accesses to peripherals and EMIF.
M2
Memory controller PMP for program cache fills from the EMIF.
M3
dMAX HiMAX master port for high-priority DMA accesses.
M4
dMAX LoMAX master port for lower-priority DMA accesses.
M5
UHPI master port for an external MCU to access on-chip and off-chip memories.
Device Overview
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