Texas Instruments TMS320C6726 사용자 설명서

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Device Configurations

3.1 Device Configuration Registers

3.2 Peripheral Pin Multiplexing Options

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors

SPRS268E – MAY 2005 – REVISED JANUARY 2007

The C672x DSP includes several device-level configuration registers, which are listed in

Table 3-1

. These

registers need to be programmed as part of the device initialization procedure. See

Section 3.2

Table 3-1. Device-Level Configuration Registers

REGISTER NAME

BYTE ADDRESS

DESCRIPTION

DEFINED

CFGPIN0

0x4000 0000

Captures values of eight pins on rising edge of RESET pin.

Table 2-10

CFGPIN1

0x4000 0004

Captures values of eight pins on rising edge of RESET pin.

Table 2-11

CFGHPI

0x4000 0008

Controls enable of UHPI and selection of its operating mode.

Table 4-12

CFGHPIAMSB

0x4000 000C

Controls upper byte of UHPI address into C672x address space in

Table 4-13

Non-Multiplexed Mode or if explicitly enabled for security purposes.

CFGHPIAUMB

0x4000 0010

Controls upper middle byte of UHPI address into C672x address space

Table 4-14

in Non-Multiplexed Mode or if explicitly enabled for security purposes.

CFGRTI

0x4000 0014

Selects the sources for the RTI Input Captures from among the six

Table 4-37

McASP DMA events.

CFGMCASP0

0x4000 0018

Selects the peripheral pin to be used as AMUTEIN0.

Table 4-19

CFGMCASP1

0x4000 001C

Selects the peripheral pin to be used as AMUTEIN1.

Table 4-20

CFGMCASP2

(1)

0x4000 0020

Selects the peripheral pin to be used as AMUTEIN2.

Table 4-21

CFGBRIDGE

0x4000 0024

Controls reset of the bridge BR2 in

Figure 2-4

. This bridge must be reset

Table 2-7

explicitly after any change to the PLL controller affecting SYSCLK1 and
SYSCLK2 and before the dMAX or UHPI accesses the CPU Slave Port
(CSP).

(1)

CFGMCASP2 is reserved on the C6722.

This section describes the options for configuring peripherals which share pins on the C672x DSP.

Table 3-2

lists the options for configuring the SPI0, I2C0, and I2C1 peripheral pins.

Table 3-2. Options for Configuring SPI0, I2C0, and I2C1

CONFIGURATION

OPTION 1

OPTION 2

OPTION 3

PERIPHERAL

SPI0

3-, 4,- or 5-pin mode

3-pin mode

disabled

I2C0

disabled

enabled

I2C1

disabled

enabled

PINS

SPI0_SOMI/I2C0_SDA

SPI0_SOMI

I2C0_SDA

SPI0_SIMO

GPIO through SPI0_SIMO pin control

SPI0_CLK/I2C0_SCL

SPI0_CLK

I2C0_SCL

SPI0_SCS/I2C1_SCL

SPI0_SCS

I2C1_SCL

SPI0_ENA/I2C1_SDA

SPI0_ENA

I2C1_SDA

Device Configurations

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