Philips S1D13505 사용자 설명서

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Epson Research and Development
Vancouver Design Center
S1D13505
Interfacing to the NEC VR4102/VR4111™ Microprocessors
X23A-G-007-06
Issue Date: 01/02/05
2  Interfacing to the VR4102/VR4111
2.1  The NEC VR4102/VR4111 System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus 
typical of modern microprocessors. Designed with external LCD controller support and 
Windows CE based embedded consumer applications in mind, the VR4102/VR4111 offers 
a highly integrated solution for portable systems. This section provides an overview of the 
operation of the CPU bus in order to establish interface requirements.
2.1.1   Overview
The NEC VR4102/VR4111 is designed around the RISC architecture developed by MIPS. 
This microprocessor is based on the 66MHz VR4100 CPU core which supports 64-bit 
processing. The CPU communicates with the Bus Control Unit (BCU) using its internal 
SysAD bus. The BCU in turn communicates with external devices using its ADD and DAT 
buses which can be dynamically sized for 16 or 32-bit operation.
The NEC VR4102/VR4111 has direct support for an external LCD controller. Specific 
control signals are assigned for an external LCD controller providing an easy interface to 
the CPU. A 16M byte block of memory is assigned for the LCD controller and its own chip 
select and ready signals are available. Word or byte accesses are controlled by the system 
high byte signal (SHB#).