Toshiba 4006GAH 사용자 설명서

360050398 

 

Toshiba Corporation Digital Media Network Company 

 

Page 138 of 157 

© 2005, Copyright TOSHIBA Corporation All Rights Reserved 

 
Word 2 bits 15:6 are reserved. 
 
Word 2 bit 5 is cleared to disable support for Ultra DMA mode 5 and has the effect of clearing bit 5 in word 88 of 
the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared if Ultra DMA 
mode 5 is currently selected.   
 
Word 2 bit 4 is cleared to disable support for Ultra DMA mode 4 and has the effect of clearing bit 4 in word 88 of 
the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared if Ultra DMA 
mode 5 is supported or if Ultra DMA mode 5 or 4 is selected. 
 
Word 2 bit 3 is cleared to disable support for Ultra DMA mode 3 and has the effect of clearing bit 3 in word 88 of 
the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared if Ultra DMA 
mode 5 or 4 is supported or if Ultra DMA mode 5, 4, or 3 is selected. 
 
Word 2 bit 2 is cleared to disable support for Ultra DMA mode 2 and has the effect of clearing bit 2 in word 88 of 
the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared if Ultra DMA 
mode 5, 4, or 3 is supported or if Ultra DMA mode 5, 4, 3, or 2 is selected. 
 
Word 2 bit 1 is cleared to disable support for Ultra DMA mode 1 and has the effect of clearing bit 1 in word 88 of 
the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared if Ultra DMA 
mode 5, 4, 3, or 2 is supported or if Ultra DMA mode 5, 4, 3, 2, or 1 is selected. 
 
Word 2 bit 0 is cleared to disable support for Ultra DMA mode 0 and has the effect of clearing bit 0 in word 88 of 
the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. This bit shall not be cleared if Ultra DMA 
mode 5, 4, 3, 2, or 1 is supported or if Ultra DMA mode 5, 4, 3, 2, 1, or 0 is selected. 
 

 
Words 3 through 6 define the maximum LBA address. This shall be the highest address accepted by the device 
after execution of the command. When this value is changed, the content of IDENTIFY DEVICE words 60, 61 
100, 101, 102, and103 shall be changed as described in the SET MAX ADDRESS and SET MAX ADDRESS 
EXT command descriptions to reflect the maximum address set with this command. This value shall not be 
changed and command aborted shall be returned if a Host Protected Area has been established by the 
execution of a SET MAX ADDRESS or SET MAX ADDRESS EXT command with an address value less than 
that returned by a READ NATIVE MAX ADDRESS or READ NATIVE MAX ADDRESS EXT command.. Any data 
contained in the Host Protected Area is not affected. 
 

 
Word 7 bits 15:9 are reserved. 
 
Word 7 bit 8 is cleared to disable support for the 48-bit Addressing feature set and has the effect of clearing bit 
10 in words 83 and 86 and clearing the value in words 103:100 of the IDENTIFY DEVICE or IDENTIFY PACKET 
DEVICE response.   
 
Word 7 bit 7 is cleared to disable support for the Host Protected Area feature set and has the effect of clearing 
bit 10 in words 82 and 85 and clearing bit 8 in words 83 and 86 of the IDENTIFY DEVICE or IDENTIFY PACKET 
DEVICE response. If a Host Protected Area has been established by use of the SET MAX ADDRESS command, 
these bits shall not be cleared and the device shall return command aborted. 
 
Word 7 bit 6 is cleared to disable for the Automatic Acoustic Management feature set and has the effect of 
clearing bit 9 in word 83 and word 94 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response. 
 
Word 7 bit 5 is cleared to disable support for the READ DMA QUEUED and WRITE DMA QUEUED commands 
and has the effect of clearing bit 1 in words 83 and 86 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE 
response.