Emerson PMPPC7448 사용자 설명서
CPLD:
Board Configuration Registers
7-6
Hardware Version Register (HVR)
Register 7-8:
Hardware Version Register (HVR) at 0xf820,7000
HVR:
Hardware Version number
This is hard coded in the PLD and changes with every major PCB version. Version starts at
00
This is hard coded in the PLD and changes with every major PCB version. Version starts at
00
16
.
PLD Version Register (PVR)
Register 7-9:
PLD Version Register (PVR) at 0xf820,8000
PVR:
PLD code Version number
This is hard coded in the PLD and changes with every major code change. Version starts at
00
This is hard coded in the PLD and changes with every major code change. Version starts at
00
16
.
BOARD CONFIGURATION REGISTERS
Three byte-wide, read-only Board Configuration registers start at location F820,9000
16
.
These registers allow the monitor software to easily determine specific hardware configu-
rations, including Monarch/non-Monarch, DMC status, Boot device, and system clock
speed.
rations, including Monarch/non-Monarch, DMC status, Boot device, and system clock
speed.
Note:
Board Configuration register 2 (0xf820,b000) is not available.
Register 7-10:
PmPPC7448 Board Configuration 3 (BCR3) at 0xf820,c000
Reserved:
Reserved for future use, default is 0
Mon:
Processor PMC Monarch indication
1 PPMC is Monarch
0 PPMC is non-Monarch
1 PPMC is Monarch
0 PPMC is non-Monarch
7
6
5
4
3
2
1
0
HVR
7
6
5
4
3
2
1
0
PVR
7
6
5
4
3
2
1
0
Reserved
Mon
DMC
R