Motorola PrPMC800/800ET Processor PMC Module 사용자 설명서
PrPMC800/800ET Processor PMC Module Installation and Use (PrPMC800A/IH5)
3 Functional Description
16
Processor
The PrPMC800/800ET board can be ordered with one of the following low-power/low care
voltage processor chips: 450 MHz MPC750-class, 450MHz or 500MHz MCP7410, or a 400
MHz MPC7410 (N).
voltage processor chips: 450 MHz MPC750-class, 450MHz or 500MHz MCP7410, or a 400
MHz MPC7410 (N).
L2 Cache
The PrPMC800/800ET
utilizes a backside L2 cache structure via the MPC750-class or
MPC7410 processor chip families. The L2 cache is implemented with an on-chip, 2-way set-
associative tag memory and external direct-mapped synchronous SRAMs for data storage. The
external SRAMs are accessed through a dedicated 72-bit wide (64 bits of data and 8 bits of
parity) L2 cache port. The MPC750-class processors support up to 1MB of L2 cache SRAMs.
The MPC7410 processor can support up to 2MB. The L2 cache can operate in copyback or
write-through modes and supports system cache coherency through snooping. Data parity
generation and checking can be disabled by programming the processor’s L2 cache control
register accordingly. The MPC7410 processor also supports direct mapping of the SRAM
memory, in conjunction with normal L2 cache operation. In this mode, a portion of the SRAM
memory space may be mapped to appear as a private memory space in the memory map.
Refer to the processor data sheet for additional information.
associative tag memory and external direct-mapped synchronous SRAMs for data storage. The
external SRAMs are accessed through a dedicated 72-bit wide (64 bits of data and 8 bits of
parity) L2 cache port. The MPC750-class processors support up to 1MB of L2 cache SRAMs.
The MPC7410 processor can support up to 2MB. The L2 cache can operate in copyback or
write-through modes and supports system cache coherency through snooping. Data parity
generation and checking can be disabled by programming the processor’s L2 cache control
register accordingly. The MPC7410 processor also supports direct mapping of the SRAM
memory, in conjunction with normal L2 cache operation. In this mode, a portion of the SRAM
memory space may be mapped to appear as a private memory space in the memory map.
Refer to the processor data sheet for additional information.
The L2 cache data SRAM for the PrPMC800/800ET is implemented using two 128K x 36 or
256K x 36 synchronous pipelined burst SRAMs providing a total of 1MB or 2MB of L2 cache,
depending on the board version.
256K x 36 synchronous pipelined burst SRAMs providing a total of 1MB or 2MB of L2 cache,
depending on the board version.
Harrier System Memory Controller / PCI Host Bridge ASIC
The Harrier ASIC provides the bridge function between the PPC60x bus, the system memory,
and the PCI Local Bus. The Harrier ASIC incorporates the following key features:
and the PCI Local Bus. The Harrier ASIC incorporates the following key features:
–
100 MHz PowerPC-compatible bus interface
–
SDRAM interface supporting up to eight banks of 512MB each, with ECC
–
32/64-bit REV2.1 compliant PCI bus interface capable of running up to 66 MHz
–
Single channel DMA controller
–
Message passing unit supporting I2O and generic functions
–
Two internal 16550-type UARTs
–
Two I
2
C bus master interfaces
–
MPIC compliant interrupt controller
–
Four Xport channels for interfacing to flash or other external registers/devices
Refer to the Harrier Programmer’s Guide for additional information and programming details.