Cypress CY7C1382D 사용자 설명서
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Document #: 38-05543 Rev. *F
Page 22 of 34
Switching Characteristics
Over the Operating Range
Parameter
Description
250 MHz
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
t
POWER
V
DD
(Typical) to the first Access
1
1
1
ms
Clock
t
t
CYC
Clock Cycle Time
4.0
5
6
ns
t
CH
Clock HIGH
1.7
2.0
2.2
ns
t
CL
Clock LOW
1.7
2.0
2.2
ns
Output Times
t
t
CO
Data Output Valid After CLK Rise
2.6
3.0
3.4
ns
t
DOH
Data Output Hold After CLK Rise
1.0
1.3
1.3
ns
t
CLZ
Clock to Low-Z
1.0
1.3
1.3
ns
t
CHZ
Clock to High-Z
2.6
3.0
3.4
ns
t
OEV
OE LOW to Output Valid
2.6
3.0
3.4
ns
t
OELZ
OE LOW to Output Low-Z
0
0
0
ns
t
OEHZ
OE HIGH to Output High-Z
2.6
3.0
3.4
ns
Setup Times
t
t
AS
Address Setup Before CLK Rise
1.2
1.4
1.5
ns
t
ADS
ADSC, ADSP Setup Before CLK Rise
1.2
1.4
1.5
ns
t
ADVS
ADV Setup Before CLK Rise
1.2
1.4
1.5
ns
t
WES
GW, BWE, BW
X
Setup Before CLK Rise
1.2
1.4
1.5
ns
t
DS
Data Input Setup Before CLK Rise
1.2
1.4
1.5
ns
t
CES
Chip Enable SetUp Before CLK Rise
1.2
1.4
1.5
ns
Hold Times
t
t
AH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
t
ADH
ADSP, ADSC Hold After CLK Rise
0.3
0.4
0.5
ns
t
ADVH
ADV Hold After CLK Rise
0.3
0.4
0.5
ns
t
WEH
GW, BWE, BW
X
Hold After CLK Rise
0.3
0.4
0.5
ns
t
DH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
t
CEH
Chip Enable Hold After CLK Rise
0.3
0.4
0.5
ns
Notes
20. Timing reference level is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
22. This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
23. t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of
on page 21. Transition is measured ± 200
mV from steady-state voltage.
24. At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
25. This parameter is sampled and not 100% tested.