Cypress CY14E102N 사용자 설명서

Document Number: 001-45755 Rev. *A

Page 4 of 21

The CY14E102L/CY14E102N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture all cells are stored and
recalled in parallel. During the STORE and RECALL operations
SRAM read and write operations are inhibited. The
CY14E102L/CY14E102N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.

The CY14E102L/CY14E102N performs a READ cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A

0-17

 

or A

0-16

 determines which of the 262, 144

data bytes or 131, 072 words of 16 bits each is accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of t

AA

. If the read is initiated by CE or OE, the

outputs are valid at t

ACE

 or at t

DOE

, whichever is later. The data

outputs repeatedly respond to address changes within the t

AA

access time without the need for transitions on any control input
pins. This remains valid until another address change or until CE
or OE is brought HIGH, or WE or HSB is brought LOW.

A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable before entering
the WRITE cycle and must remain stable until either CE or WE
goes high at the end of the cycle. The data on the common IO
pins DQ

0–15

 are written into the memory if the data is valid t

SD

before the end of a WE controlled WRITE or before the end of
an CE controlled WRITE. It is recommended that OE be kept
HIGH during the entire WRITE cycle to avoid data bus contention
on common IO lines. If OE is left LOW, internal circuitry turns off
the output buffers t

HZWE 

after WE goes LOW.

The CY14E102L/CY14E102N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB, Software Store activated by an address
sequence, and AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14E102L/CY14E102N.

During a normal operation, the device draws current from V

CC

 to

charge a capacitor connected to the V

CAP

 pin. This stored

charge is used by the chip to perform a single STORE operation.
If the voltage on the V

CC

 pin drops below V

SWITCH

, the part

automatically disconnects the V

CAP

 pin from V

CC

. A STORE

operation is initiated with power provided by the V

CAP

 capacitor.

shows the proper connection of the storage capacitor

(V

CAP

) for automatic store operation. Refer to the section 

 on page 7 for the size of V

CAP 

. 

To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. Monitor the HSB signal by the system to detect if an
AutoStore cycle is in progress. 

The CY14E102L/CY14E102N provides the HSB pin for
controlling and acknowledging the STORE operations. Use the
HSB pin to request a hardware STORE cycle. When the HSB pin
is driven LOW, the CY14E102L/CY14E102N conditionally
initiates a STORE operation after t

DELAY

. An actual STORE cycle

only begins if a WRITE to the SRAM took place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition while the STORE (initiated by any means) is in
progress.

SRAM READ and WRITE operations that are in progress when
HSB is driven LOW by any means are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14E102LL/CY14E102N continues SRAM operations for
t

DELAY

. During t

DELAY

, multiple SRAM READ operations may take

place. If a WRITE is in progress when HSB is pulled low it is
allowed a time, t

DELAY

 to complete. However, any SRAM WRITE

cycles requested after HSB goes LOW is inhibited until HSB
returns HIGH.

During any STORE operation, regardless of how it was initiated,
the CY14E102L/CY14E102N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the
CY14E102L/CY14E102N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.