Texas Instruments TMS320C6454 사용자 설명서
www.ti.com
PRODUCT PREVIEW
3.2 Peripheral Configuration at Device Reset
TMS320C6454
Fixed-Point Digital Signal Processor
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Table 3-1. C6454 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued)
CONFIGURATION
IPD/
NO.
FUNCTIONAL DESCRIPTION
PIN
IPU
(1)
PCI pin function enable bit (PCI_EN).
Selects which function is enabled on the HPI/PCI multiplexed pins.
Selects which function is enabled on the HPI/PCI multiplexed pins.
0
HPI pin function enabled (default)
PCI_EN
Y29
IPD
This means all multiplexed HPI/PCI pins function as HPI pins.
1
PCI pin function enabled
This means all multiplexed HPI/PCI pins function as PCI pins.
This means all multiplexed HPI/PCI pins function as PCI pins.
DDR2 Memory Controller enable (DDR2_EN).
ABA0
V26
IPD
0
DDR2 Memory Controller peripheral pins are disabled (default)
1
DDR2 Memory Controller peripheral pins are enabled
EMIFA enable (EMIFA_EN).
ABA1
V25
IPD
0
EMIFA peripheral pins are disabled (default)
1
EMIFA peripheral pins are enabled
Some C6454 peripherals share the same pins (internally multiplexed) and are mutually exclusive.
Therefore, not all peripherals may be used at the same time. The device configuration pins described in
Therefore, not all peripherals may be used at the same time. The device configuration pins described in
, Device Configuration at Device Reset, determine which function is enabled for the multiplexed
pins.
Note that when the pin function of a peripheral is disabled at device reset, the peripheral is permanently
disabled and cannot be enabled until its pin function is enabled and another device reset is executed.
Also, note that enabling the pin function of a peripheral does not enable the corresponding peripheral. All
peripherals on the C6454 device are disabled by default, except when used for boot, and must be enabled
through software before being used.
disabled and cannot be enabled until its pin function is enabled and another device reset is executed.
Also, note that enabling the pin function of a peripheral does not enable the corresponding peripheral. All
peripherals on the C6454 device are disabled by default, except when used for boot, and must be enabled
through software before being used.
Other peripheral options like PCI clock speed and EMAC/MDIO interface mode can also be selected at
device reset through the device configuration pins. The configuration selected is also fixed at device reset
and cannot be changed until another device reset is executed with a different configuration selected.
device reset through the device configuration pins. The configuration selected is also fixed at device reset
and cannot be changed until another device reset is executed with a different configuration selected.
The multiply factor of the PLL1 Controller is not selected through the configuration pins. The PLL1 multiply
factor is set in software through the PLL1 controller registers after device reset. The PLL2 multiply factor is
fixed. For more information, see
factor is set in software through the PLL1 controller registers after device reset. The PLL2 multiply factor is
fixed. For more information, see
, PLL1 and PLL1 Controller, and
,PLL2 and PLL2
Controller.
On the C6454 device, the PCI peripheral pins are multiplexed with the HPI pins. The PCI_EN pin selects
the function for the HPI/PCI multiplexed pins. The PCI66, PCI_EEAI, and HPI_WIDTH control other
functions of the PCI and HPI peripherals.
the function for the HPI/PCI multiplexed pins. The PCI66, PCI_EEAI, and HPI_WIDTH control other
functions of the PCI and HPI peripherals.
describes the effect of the PCI_EN, PCI66, PCI_EEAI,
and HPI_WIDTH configuration pins.
Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI)
CONFIGURATION PIN SETTING
(1)
PERIPHERAL FUNCTION SELECTED
PCI66
PCI_EEAI
HPI_WIDTH
PCI_EN PIN
HPI DATA
HPI DATA
32-BIT PCI
PCI
AEA6 PIN
AEA8 PIN
AEA14 PIN
[Y29]
LOWER
UPPER
(66-/33-MHz)
AUTO-INIT
[U27]
[P25]
(1)
[R25]
0
0
0
0
Enabled
Hi-Z
Disabled
N/A
0
0
0
1
Enabled
Enabled
Disabled
N/A
Enabled
1
1
1
X
Disabled
(via External I2C
Enabled
EEPROM)
(66 MHz)
1
1
0
X
Disabled
Disabled
(1)
PCI_EEAI is latched at reset as a configuration input. If PCI_EEAI is set as one, then default values are loaded from an external I2C
EEPROM.
EEPROM.
Device Configuration
52