Texas Instruments TMS320C6454 사용자 설명서
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PRODUCT PREVIEW
5
C64x+ Megamodule
A register file
Data path 1
Data path 2
B register file
D2
S2
xx
xx
M2
L2
Instruction decode
M1
xx
xx
L1
S1
D1
16/32−bit instruction dispatch
Instruction fetch
SPLOOP buffer
64
64
C64x+ CPU
256
32
L1D cache/SRAM
Bandwidth management
Memory protection
L1 data memory controller
IDMA
256
256
Bandwidth management
L1 program memory controller
Memory protection
256
Advanced event
triggering
(AET)
Interrupt
and exception
controller
Power control
L2 memory
controller
256
256
Master DMA
Slave DMA
128
256
L1P cache/SRAM
L2
cache/
SRAM
SRAM
256
128
128
To primary
switch fabric
Cache
control
Bandwidth
management
Memory
protection
Cache control
Cache control
Internal
ROM
(A)
256
Configuration
Registers
32
To Chip
registers
External memory
controller
A. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
5.1 Memory Architecture
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
The C64x+ Megamodule consists of several components — the C64x+ CPU, the L1 program and data
memory controllers, the L2 memory controller, the internal DMA (IDMA), the interrupt controller,
power-down controller, and external memory controller. The C64x+ Megamodule also provides support for
memory protection (for L1P, L1D, and L2 memories) and bandwidth management (for resources local to
the C64x+ Megamodule).
memory controllers, the L2 memory controller, the internal DMA (IDMA), the interrupt controller,
power-down controller, and external memory controller. The C64x+ Megamodule also provides support for
memory protection (for L1P, L1D, and L2 memories) and bandwidth management (for resources local to
the C64x+ Megamodule).
shows a block diagram of the C64x+ Megamodule.
Figure 5-1. 64x+ Megamodule Block Diagram
For more detailed information on the TMS320C64x+ Megamodule on the C6454 device, see the
TMS320C64x+ Megamodule Reference Guide (literature number
TMS320C64x+ Megamodule Reference Guide (literature number
The TMS320C6454 device contains a 1048KB level-2 memory (L2), a 32KB level-1 program memory
(L1P), and a 32KB level-1 data memory (L1D).
(L1P), and a 32KB level-1 data memory (L1D).
The L1P memory configuration for the C6454 device is as follows:
•
Region 0 size is 0K bytes (disabled).
•
Region 1 size is 32K bytes with no wait states.
The L1D memory configuration for the C6454 device is as follows:
•
Region 0 size is 0K bytes (disabled).
C64x+ Megamodule
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