Texas Instruments TMS320DM646x 사용자 설명서
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5.29 MAC Control Register (MACCONTROL)
Ethernet Media Access Controller (EMAC) Registers
The MAC control register (MACCONTROL) is shown in
and described in
.
Figure 69. MAC Control Register (MACCONTROL)
31
18
17
16
Reserved
GIGFORCE
Reserved
R-0
R/W-0
R-0
15
14
13
12
11
10
9
8
Reserved
RXOFFLENBLOCK
RXOWNERSHIP
RXFIFOFLOWEN
CMDIDLE
Rsvd
TXPTYPE
Reserved
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R-0
7
6
5
4
3
2
1
0
GIG
TXPACE
GMIIEN
TXFLOWEN
RXBUFFERFLOWEN
Rsvd
LOOPBACK
FULLDUPLEX
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 68. MAC Control Register (MACCONTROL) Field Descriptions
Bit
Field
Value
Description
31-18
Reserved
0
Reserved
17
GIGFORCE
0-1
Gigabit force mode. This bit is used to force the EMAC into gigabit mode, if the MTCLK input
signal has been stopped by the PHY.
signal has been stopped by the PHY.
16-15
Reserved
0
Reserved
14
RXOFFLENBLOCK
Receive offset/length word write block.
0
Do not block the DMA writes to the receive buffer descriptor offset/buffer length word.
1
Block all EMAC DMA controller writes to the receive buffer descriptor offset/buffer length
words during packet processing. When this bit is set, the EMAC will never write the third word
to any receive buffer descriptor.
words during packet processing. When this bit is set, the EMAC will never write the third word
to any receive buffer descriptor.
13
RXOWNERSHIP
Receive ownership write bit value.
0
EMAC writes the Receive ownership bit to 0 at the end of packet processing.
1
EMAC writes the Receive ownership bit to 1 at the end of packet processing. If you do not use
the ownership mechanism, you can set this mode to preclude the necessity of software having
to set this bit each time the buffer descriptor is used.
the ownership mechanism, you can set this mode to preclude the necessity of software having
to set this bit each time the buffer descriptor is used.
12
RXFIFOFLOWEN
Receive FIFO flow control enable bit.
0
Receive flow control is disabled. Full-duplex mode: no outgoing pause frames are sent.
1
Receive flow control is enabled. Full-duplex mode: outgoing pause frames are sent when
receive FIFO flow control is triggered.
receive FIFO flow control is triggered.
11
CMDIDLE
Command Idle bit.
0
Idle is not commanded.
1
Idle is commanded (read the IDLE bit in the MACSTATUS register).
10
Reserved
0
Reserved
9
TXPTYPE
Transmit queue priority type.
0
The queue uses a round-robin scheme to select the next channel for transmission.
1
The queue uses a fixed-priority (channel 7 is highest priority) scheme to select the next
channel for transmission.
channel for transmission.
8
Reserved
0
Reserved
7
GIG
Gigabit mode bit.
0
Gigabit mode is disabled; 10/100 mode is in operation.
1
Gigabit mode is enabled (full-duplex only).
6
TXPACE
Transmit pacing enable bit.
0
Transmit pacing is disabled.
1
Transmit pacing is enabled.
110
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
SPRUEQ6 – December 2007