Texas Instruments TMS320DM646x 사용자 설명서
www.ti.com
5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)
5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)
Ethernet Media Access Controller (EMAC) Registers
The transmit channel 0-7 completion pointer register (TXnCP) is shown in
and described in
Figure 88. Transmit Channel n Completion Pointer Register (TXnCP)
31
16
TXnCP
R/W-x
15
0
TXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 87. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
Bit
Field
Value
Description
31-0
TXnCP
0-FFFF FFFFh
Transmit channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
The receive channel 0-7 completion pointer register (RXnCP) is shown in
and described in
Figure 89. Receive Channel n Completion Pointer Register (RXnCP)
31
16
RXnCP
R/W-x
15
0
RXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 88. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
Bit
Field
Value
Description
31-0
RXnCP
0-FFFF FFFFh
Receive channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
SPRUEQ6 – December 2007
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
123