Texas Instruments TMS320DM646x 사용자 설명서
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3.5
EMAC Control Module Receive Threshold Interrupt Enable Register
3.6
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
EMAC Control Module Registers
(CMRXTHRESHINTEN)
The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in
and
described in
Figure 17. EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXTHRESHEN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN) Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXTHRESHEN[n]
Receive threshold interrupt (RXTHRESHPENDn) enable. Each bit controls the corresponding
channel n receive threshold interrupt.
channel n receive threshold interrupt.
Bit n = 0, channel n receive threshold interrupt (RXTHRESHPENDn) is disabled.
Bit n = 1, channel n receive threshold interrupt (RXTHRESHPENDn) is enabled.
The receive interrupt enable register (CMRXINTEN) is shown in
and described in
Figure 18. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
31
16
Reserved
R-0
15
8
7
0
Reserved
RXPULSEEN
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
0
Reserved
7-0
RXPULSEEN[n]
Receive interrupt (RXPENDn) enable. Each bit controls the corresponding channel n receive
interrupt.
interrupt.
Bit n = 0, channel n receive interrupt (RXPENDn) is disabled.
Bit n = 1, channel n receive interrupt (RXPENDn) is enabled.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
64
SPRUEQ6 – December 2007