Texas Instruments TMS320DM643 사용자 설명서
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2.4.6
Mode Register Set (MRS and EMRS)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BA[2:0]
COL
MRS/EMRS
DDR_A[12:0]
DDR_CAS
BANK
DDR_CLK
Peripheral Architecture
DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for
operation. These registers control burst type, burst length, CAS latency, DLL enable/disable (on DDR2
device), single-ended strobe, etc.
operation. These registers control burst type, burst length, CAS latency, DLL enable/disable (on DDR2
device), single-ended strobe, etc.
The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by
issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on
DDR_BA[1:0] selects the mode register to be written and the data on DDR_A[12:0] is loaded into the
register.
issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on
DDR_BA[1:0] selects the mode register to be written and the data on DDR_A[12:0] is loaded into the
register.
shows the timing for an MRS and EMRS command.
The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controller
initialization sequence. See
initialization sequence. See
for more information.
Figure 10. DDR2 MRS and EMRS Command
SPRU986B – November 2007
DDR2 Memory Controller
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