Texas Instruments TMS320DM643 사용자 설명서
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4.4
SDRAM Timing Register (SDTIMR)
DDR2 Memory Controller Registers
The SDRAM timing register (SDTIMR) configures the DDR2 memory controller to meet many of the AC
timing specification of the DDR2 memory. The SDTIMR register is programmable only when the
TIMUNLOCK bit is set to 1 in the SDBCR. Note that DDR_CLK is equal to the period of the DDR_CLK
signal. See the DDR2 memory data sheet for information on the appropriate values to program each field.
The SDTIMR is shown in
timing specification of the DDR2 memory. The SDTIMR register is programmable only when the
TIMUNLOCK bit is set to 1 in the SDBCR. Note that DDR_CLK is equal to the period of the DDR_CLK
signal. See the DDR2 memory data sheet for information on the appropriate values to program each field.
The SDTIMR is shown in
and described in
Figure 22. SDRAM Timing Register (SDTIMR)
31
25
24
22
21
19
18
16
T_RFC
T_RP
T_RCD
T_WR
R/W-1Ah
R/W-5h
R/W-5h
R/W-3h
15
11
10
6
5
3
2
1
0
T_RAS
T_RC
T_RRD
Rsvd
T_WTR
R/W-9h
R/W-Eh
R/W-3h
R-0
R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. SDRAM Timing Register (SDTIMR) Field Descriptions
Bit
Field
Value
Description
31-25
T_RFC
0-7Fh
Specifies the minimum number of DDR_CLK cycles from a refresh or load mode command to a refresh
or activate command, minus 1. Corresponds to the t
or activate command, minus 1. Corresponds to the t
rfc
AC timing parameter in the DDR2 data sheet.
Calculate by:
T_RFC = (t
rfc
/DDR_CLK period) - 1
24-22
T_RP
0-7h
Specifies the minimum number of DDR_CLK cycles from a precharge command to a refresh or activate
command, minus 1. Corresponds to the t
command, minus 1. Corresponds to the t
rp
AC timing parameter in the DDR2 data sheet. Calculate by:
T_RP = (t
rp
/DDR_CLK period) - 1
21-19
T_RCD
0-7h
Specifies the minimum number of DDR_CLK cycles from an activate command to a read or write
command, minus 1. Corresponds to the t
command, minus 1. Corresponds to the t
rcd
AC timing parameter in the DDR2 data sheet. Calculate by:
T_RCD = (t
rcd
/DDR_CLK period) - 1
18-16
T_WR
0-7h
Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge
command, minus 1. Corresponds to the t
command, minus 1. Corresponds to the t
wr
AC timing parameter in the DDR2 data sheet. Calculate by:
T_WR = (t
wr
/DDR_CLK period) - 1
When the value of this field is changed from its previous value, the initialization sequence will begin.
15-11
T_RAS
0-1Fh
Specifies the minimum number of DDR_CLK cycles from an activate command to a precharge
command, minus 1. Corresponds to the t
command, minus 1. Corresponds to the t
ras
AC timing parameter in the DDR2 data sheet. Calculate by:
T_RAS = (t
ras
/DDR_CLK period) - 1
T_RAS must be greater than or equal to T_RCD.
10-6
T_RC
0-1Fh
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate
command, minus 1. Corresponds to the t
command, minus 1. Corresponds to the t
rc
AC timing parameter in the DDR2 data sheet. Calculate by:
T_RC = (t
rc
/DDR_CLK period) - 1
5-3
T_RRD
0-7h
Specifies the minimum number of DDR_CLK cycles from an activate command to an activate command
in a different bank, minus 1. Corresponds to the t
in a different bank, minus 1. Corresponds to the t
rrd
AC timing parameter in the DDR2 data sheet.
Calculate by:
T_RRD = (t
rrd
/DDR_CLK period) - 1
Note: for an 8 bank DDR2 device this field must be equal to ((4
×
t
RRD
) + (2
×
t
CK
)) / (4
×
t
CK
) - 1.
2
Reserved
0
Reserved
1-0
T_WTR
0-3h
Specifies the minimum number of DDR_CLK cycles from the last write to a read command, minus 1.
Corresponds to the t
Corresponds to the t
wtr
AC timing parameter in the DDR2 data sheet. Calculate by:
T_WTR = (t
wtr
/DDR_CLK period) - 1
SPRU986B – November 2007
DDR2 Memory Controller
45