Texas Instruments TMS320DM643 사용자 설명서
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4.9
Interrupt Mask Set Register (IMSR)
DDR2 Memory Controller Registers
The interrupt mask set register (IMSR) enables the DDR2 memory controller interrupt. The IMSR is shown
in
in
and described in
.
Note:
If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in the interrupt mask clear
register (IMCR), the interrupt is not enabled and neither bit is set to 1.
register (IMCR), the interrupt is not enabled and neither bit is set to 1.
Figure 27. Interrupt Mask Set Register (IMSR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
LTMSET
Reserved
R-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. Interrupt Mask Set Register (IMSR) Field Descriptions
Bit
Field
Value
Description
31-3
Reserved
0
Reserved
2
LTMSET
Line trap interrupt set. Write a 1 to set LTMSET and the LTMCLR bit in the interrupt mask clear register
(IMCR); a write of 0 has no effect.
(IMCR); a write of 0 has no effect.
0
Line trap interrupt is not enabled; a write of 1 to the LTMCLR bit in IMCR occurred.
1
Line trap interrupt is enabled.
1-0
Reserved
0
Reserved
50
DDR2 Memory Controller
SPRU986B – November 2007