Konica Minolta PCI-1712 사용자 설명서
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APPENDIX D
PCI-1712/1712L User’s Manual
Advantech Co., Ltd.
www.advantech.com
www.advantech.com
D.14 Counter gate and clock control/status
—
Write/
Read BASE+20 to 26
Table D-15: Register for counter gate and clock control/status
Cn1 to Cn0 Counter clock source control register n = 0,1,2
Table D-16 : Table of Cn1 to Cn0 register
[Cn1: Cn0] = [0, 0], write CQn to set the counter clock. Refer
to CQn description.
to CQn description.
[Cn1: Cn0] = [0, 1], The internal clock is generated by an on-
board oscillator.
board oscillator.
[Cn1: Cn0] = [1, 0], External clock is on connector
CNTn_CLK (n = 0, 1, 2).
CNTn_CLK (n = 0, 1, 2).
[Cn1: Cn0] = [1, 1], The clock source of every counter
1
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/
N