Konica Minolta PCI-1712 사용자 설명서
– 39 –
Chapter 5
PCI-1712/1712L User’s Manual
Advantech Co., Ltd.
www.advantech.com
www.advantech.com
the PCLD-8712 screw terminal board. The trigger signal is TTL-
compatible.
compatible.
q Analog Threshold Trigger
For analog input operations, an analog trigger event occurs when the
PCI-1712/1712L detects a transition from above a threshold level to
below a threshold level (falling edge), or a transition from below a
threshold level to above a threshold level (rising edge). User should
connect analog signals from external device or internal analog output
channel on board to external screw terminal ANA_TRG on the PCLD-
8712 screw terminal board.
For analog input operations, an analog trigger event occurs when the
PCI-1712/1712L detects a transition from above a threshold level to
below a threshold level (falling edge), or a transition from below a
threshold level to above a threshold level (rising edge). User should
connect analog signals from external device or internal analog output
channel on board to external screw terminal ANA_TRG on the PCLD-
8712 screw terminal board.
On the PCI-1712/1712L, the threshold level is set using a dedicated 8-
bit DAC; the hysteresis is fixed at 50 mV. Using software, you can
program the threshold level by writing a voltage value to this DAC;
this value can range from -10 V to +10 V.
bit DAC; the hysteresis is fixed at 50 mV. Using software, you can
program the threshold level by writing a voltage value to this DAC;
this value can range from -10 V to +10 V.
Analog Input Data Format
Table 5-2: Analog Input Data Format
Table 5-3: The corresponding Full Scale values for various Input
Voltage Ranges
e
d
o
c
D
/
A
e
g
a
t
l
o
V
g
n
i
p
p
a
M
.
x
e
H
.
c
e
D
r
a
l
o
p
i
n
U
r
a
l
o
p
i
B
h
0
0
0
d
0
0
2
/
S
F
-
h
F
F
7
d
7
4
0
2
B
S
L
1
-
2
/
S
F
B
S
L
1
-
h
0
0
8
d
8
4
0
2
2
/
S
F
0
h
F
F
F
d
5
9
0
4
B
S
L
1
-
S
F
B
S
L
1
-
2
/
S
F
B
S
L
1
6
9
0
4
/
S
F
6
9
0
4
/
S
F
n
i
a
G
r
a
l
p
i
n
U
r
a
l
o
p
i
B
e
g
n
a
R
S
F
e
g
n
a
R
S
F
5
.
0
A
/
N
A
/
N
V
0
1
±
0
2
1
V
0
1
~
0
0
1
V
5
±
0
1
2
V
5
~
0
5
V
5
.
2
±
5
4
V
5
.
2
~
0
5
.
2
V
5
2
.
1
±
5
.
2
8
V
5
2
.
1
~
0
5
2
.
1
V
5
2
6
.
0
±
5
2
.
1