Fujitsu FR81 사용자 설명서

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FUJITSU MICROELECTRONICS LIMITED

CM71-00105-1E

CHAPTER 4  RESET AND "EIT" PROCESSING
4.9

After the interrupt request for a general interrupt has been accepted in the CPU as EIT following its

generation, the control moves to the interrupt processing routine after the execution of the EIT sequence.

Vector numbers are assigned to each source of general interrupts, and the interrupt processing routine

corresponding to these vector numbers are started. The interrupt sources and vector numbers do not

necessarily have a one-to-one correspondence, and at times the same vector number is assigned to multiple

interrupt sources. In such a case, the same interrupt processing routine is used for multiple interrupt

sources.

Right in the beginning of the interrupt processing routine, the flag bit which indicates an interrupt source is

verified. If the flag bit has been set, interrupt request for that interrupt is generated and the required

processing (program) is executed after clearing the flag bit. In case, the same vector offset is being used for

multiple interrupt sources, there are multiple flag bits indicating interrupt sources, and each of them are

identified and processed in the same manner.

It is necessary to clear the flag bit while the interrupt of that particular interrupt source is in the disabled

state. When the interrupt processing routine is started after the execution of the EIT sequence, the interrupt

level of the general interrupt is stored in the interrupt level mask register (ILM) and the general interrupt of

that interrupt level is disabled. Make sure to clear the flag bit at the end of the interrupt processing without

modifying the interrupt level mask register (ILM).

The control is returned from the interrupt processing routine by the RETI instruction.

Interrupt requests are enabled either when the corresponding flag bit has been cleared, or at the time of

clearing the flag bit. Enabling interrupt requests when the flag bit is in the set state, leads to the generation

of interrupt request immediately.

While enabling interrupt requests, do not clear flag bit besides the interrupt processing routine. Flag bit

should be cleared at the time of disabling interrupt request.

In case a flag bit is cleared when a peripheral function is performing an operation, there are times when the

flag bit cannot be cleared if the clearing of flag bit by writing to the register and the occurrence of a

phenomenon which can be an interrupt source take place simultaneously or at a very close interval.

Whether a flag bit will be cleared or not when the clearing of flag bit and the occurrence of a phenomenon

that can become an interrupt source take place simultaneously, differs from one peripheral function to the

other.