Fujitsu FR81S 사용자 설명서
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
8.2.
System Register.............................................................................................................. 115
9.
R
ESET AND
EIT
P
ROCESSING
........................................................................................................ 116
9.1.
Reset ............................................................................................................................... 117
9.2.
EIT Processing ................................................................................................................ 118
9.3.
Vector Table .................................................................................................................... 119
10.
M
EMORY
P
ROTECTION
F
UNCTION
(MPU) ..................................................................................... 121
10.1.
Overview ........................................................................................................................ 122
10.2.
List of Registers ............................................................................................................. 123
10.3.
Description of Registers ................................................................................................. 124
10.3.1.
MPU Control Register : MPUCR ........................................................................................................... 125
10.3.2.
Instruction Access Protection Violation Address Register : IPVAR................................................... 128
10.3.3.
Instruction Access Protection Violation Status Register : IPVSR ...................................................... 129
10.3.4.
Data Access Protection Violation Address Register :DPVAR ............................................................ 131
10.3.5.
Data Access Protection Violation Status Register : DPVSR .............................................................. 132
10.3.6.
Data Access Error Address Register : DEAR ...................................................................................... 134
10.3.7.
Data Access Error Status Register : DESR .......................................................................................... 135
10.3.8.
Protection Area Base Address Register 0 to 7 : PABR0 to PABR7 .................................................. 137
10.3.9.
Protection Area Control Register 0 to 7 : PACR0 to PACR7 ............................................................. 138
10.4.
Operations of Memory Protection Function ................................................................... 142
10.4.1.
Setting Up Memory Protection Areas .................................................................................................... 143
10.4.2.
Instruction Access Protection Violation ................................................................................................. 144
10.4.3.
Data Access Protection Violation........................................................................................................... 145
10.4.4.
Data Access Errors .................................................................................................................................. 146
10.4.5.
Memory Protection Operation by Delay Slot........................................................................................ 147
10.4.6.
DEAR and DESR Update ....................................................................................................................... 148
10.4.7.
Notes ......................................................................................................................................................... 149
CHAPTER 4: OPERATION MODE ..................................................................................................... 151
1.
O
VERVIEW
.................................................................................................................................. 152
2.
F
EATURES
................................................................................................................................... 153
3.
C
ONFIGURATION
.......................................................................................................................... 154
4.
R
EGISTER
................................................................................................................................... 155
4.1.
Bus Mode Register : BMODR (Bus MODe Register) .................................................... 156
5.
O
PERATION
................................................................................................................................. 157
5.1.
MD0, MD1, P006 Pins Settings ..................................................................................... 158
5.2.
Fetching the Operation Mode ........................................................................................ 159
5.3.
Explanation of Each Operation Mode ............................................................................ 160
5.3.1.
User Mode ................................................................................................................................................ 161
5.3.2.
Serial Writer Mode ................................................................................................................................... 162
CHAPTER 5: CLOCK ......................................................................................................................... 163
1.
O
VERVIEW
.................................................................................................................................. 164
2.
F
EATURES
................................................................................................................................... 166
3.
C
ONFIGURATION
.......................................................................................................................... 167
4.
R
EGISTERS
................................................................................................................................. 171
4.1.
Division Configuration Register 0 : DIVR0 (Division clock configuration Register 0) .... 172
4.2.
Division Configuration Register 1 : DIVR1 (Division clock configuration Register 1) .... 173
4.3.
Division Configuration Register 2 : DIVR2 (Division clock configuration Register 2) .... 174
4.4.
Clock Source Selection Register : CSELR (Clock source Selection Register) ............. 175
4.5.
Clock Source Monitor Register : CMONR (Clock source MONitor Register) ................ 178
4.6.
Main Timer Control Register : MTMCR (Main clock TiMer Control Register) ................ 180
4.7.
Sub Timer Control Register : STMCR (Sub clock TiMer Control Register) ................... 182
4.8.
PLL Setting Register : PLLCR (PLL Configuration Register)......................................... 184
4.9.
Clock Stabilization Selection Register : CSTBR (Clock STaBilization selection Register)
...................................................................................................................................... 187
4.10.
PLL Oscillation Timer Control Register : PTMCR (PLL clock osc TiMer Control Register)
...................................................................................................................................... 189
4.11.
PLL/SSCG Clock Selection Register : CCPSSELR (CCtl Pll/Sscg clock Selection
Register) ....................................................................................................................... 190
MB91520 Series
MN705-00010-1v0-E
(10)