Fujitsu FR81S 사용자 설명서
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
10.3.2.
Instruction Access Protection Violation Address
Register : IPVAR
Register : IPVAR
The bit configuration of the instruction access protection violation address register is shown.
This register stores the address where an instruction access protection violation occurred.
Also see "10.4.2. Instruction Access Protection Violation" and "10.4.7. Notes".
IPVAR : Address 0318
H
(Access: Word)
bit31
bit30
• • •
bit2
bit1
bit0
IPVA[31:0]
Initial value
X
X
• • •
X
X
X
Attribute R,WX R,WX
• • •
R,WX R,WX R,WX
[bit31 to bit0] IPVA[31:0] (Instruction fetch Protection Violation Address)
This register stores the address where an instruction access protection violation occurred when a violation
has not occurred in the instruction access protection violation status register (IPVSR.IPV =0). This is not
aligned.
Note:
This register is a prohibition of use.
MB91520 Series
MN705-00010-1v0-E
128