Fujitsu FR81S 사용자 설명서
CHAPTER 48: WAVEFORM GENERATOR
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WAVEFORM GENERATOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
19
4.1.3. 16-bit Dead Timer Reload Interrupt Register (DTIR)
The bit configuration for the 16-bit dead timer reload Interrupt register is shown below.
The 16-bit dead timer reload interrupt register (DTIR) is used to control the interrupt request when the timer is
reloaded before it underflows as well as to control the interrupt request enable.
DTIR0: Address 12AD
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DTRIF2 DTRIE2
DTRIF1
DTRIE1
DTRIF0 DTRIE0
Reserved
Initial values
0
0
0
0
0
0
0
0
Attributes R(RM1),
W
R/W
R(RM1),
W
R/W
R(RM1),
W
R/W
R0,W0 R0,W0
[bit7] DTRIF2: 16-bit dead timer 2 reload interrupt flag bit
DTRIF2
Function
Read
Write
0
No reload of the dead timer has been
detected.
This bit is cleared.
1
A reload of the dead timer has been detected.
This bit remains unaffected.
⋅
For the 16-bit dead timer 2, if the timer is reloaded before it underflows, this bit will be set to "1".
⋅
An interrupt request is generated when this bit and the interrupt request enable bit (DTIR: DTRIE2) are
"1".
⋅
This bit is cleared when "0" is written to it. A write of "1" does not change this bit and has no influence
on others.
⋅
This bit will be cleared when the dead timer interrupt clear signal is "H".
Notes:
If this bit is read by a read-modify-write (RMW) instruction, "1" is always read.
If a software clear (write of "0") or a clear by an interrupt clear signal ("H") and a hardware set occur at the
same time, the hardware set has a priority over the software clear or the clear by interrupt clear signal.
Then, this bit will be set.
[bit6] DTRIE2: 16-bit dead timer 2 reload interrupt enable bit
DTRIE2
Function
0
An interrupt will not be generated even when a reload occurs at the 16-bit dead timer.
1
An interrupt will be generated when a reload occurs at the 16-bit dead timer.
⋅
This bit enables or disables the output of interrupts to the CPU.
⋅
An interrupt request is generated when this bit and the interrupt request flag bit (DTIR: DTRIF2) are "1".
[bit5] DTRIF1: 16-bit dead timer 1 reload interrupt flag bit
DTRIF1
Function
Read
Write
0
No reload of the dead timer has been
detected.
This bit is cleared.
1
A reload of the dead timer has been detected.
This bit remains unaffected.
⋅
For the 16-bit dead timer 1, if the timer is reloaded before it underflows, this bit will be set to "1".
⋅
An interrupt request is generated when this bit and the interrupt request enable bit (DTIR: DTRIE1) are
"1".
⋅
This bit is cleared when "0" is written to it. A write of "1" does not change this bit and has no influence
on others.
MB91520 Series
MN705-00010-1v0-E
2064