Fujitsu FR81S 사용자 설명서
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
56
Notes:
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In debug operation (E_DBCR:PLOCK =1), PLL cannot stop because always supplying the PLL clock is
required for MDI communication.
⋅
Interrupts cannot be transferred normally in switching PLL-SSCG. Therefore, when switching PLL-SSCG
synchronous/asynchronous, disable the interrupt from resource.
⋅
The PLL/SSCG macro oscillation clock frequency has the upper bound and the lower bound.
Set the multiplication rate of PLL/SSCG so as not to exceed the following range.
PLL/SSCG in Microcontroller unit :
⋅
200MHz ≤ PLL macro oscillation clock frequency ≤ 320MHz
⋅
200MHz ≤ SSCG macro oscillation clock frequency ≤ 320MHz (Down Speed)
MB91520 Series
MN705-00010-1v0-E
217