Fujitsu FR81S 사용자 설명서
CHAPTER 7: RESET
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
36
The following describes each reset issue sequence after reset factors of this reset have been
released.
Figure 5-2 Super Initialize Reset (SINIT) Sequence
INIT
Factor
RST
Oscillation stabilization wait time + (PCLK × 4 cycles)
*: PCLK × (1026+3) cycles
PCLK × 16 cycles
OCDU chip reset
sequence*
Because the clock settings register is initialized by reset, the period of the peripheral clock
(PCLK) is 8 times the period of the main clock (MCLK).
MB91520 Series
MN705-00010-1v0-E
289