Fujitsu FR81S 사용자 설명서
CHAPTER 22: 32-BIT OUTPUT COMPARE
6. Setting
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
6. Setting
This section explains settings of the 32-bit output compare.
Table 6-1 Configuration Necessary for Use of Output Compare
Configuration
Register to be configured
Setting
Method
Setting of the free-run timer
See "CHAPTER: 32-BIT FREE-RUN
TIMER".
-
Setting of the compare value
Compare register: (OCCPx)
See 7.1.
Setting of the compare mode
Output control register (OCSHxx, OCSLxx)
See 7.2.
Compare operation stop
See 7.3.
Setting of the compare pin output initial level
See 7.4.
Setting of OCU6, OCU7 pins to output
Set each pin for peripheral output.
See "CHAPTER: I/O PORTS", for the setting method.
The free-run timer clear
Timer control register (TCCS)
See "CHAPTER: 32-BIT FREE-RUN
TIMER ".
See 7.6.
Compare operation enable (activation)
Output control register (OCSHxx, OCSLxx)
See 7.7.
Operation mode selection
Output level control register (OCLS)
See 7.12.
Table 6-2 Items Necessary for Interrupt Execution
Configuration
Register to be configured
Setting
Method
Setting of output compare interrupt vector
and output compare interrupt level
See "CHAPTER: INTERRUPT CONTROL
(
INTERRUPT CONTROLLER)".
See 7.8.
Setting of output compare interrupt
Interrupt request clear
Interrupt request enable
Output control register (OCSHxx, OCSLxx)
See 7.10.
MB91520 Series
MN705-00010-1v0-E
858