Fujitsu FR81S 사용자 설명서
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
196
[1] Master operation (Set SCR:MS=0, SMR:SCKE=1, SCSCR:CSOE=1, SCSCR:CSENn*=1)
*: "n" shows the number of serial chip select pin used.
Transmission operation
(1) With serial data output enabled (SMR:SOE=1), transmission operation enabled (SCR:TXE=1), and
reception operation disabled (SCR:RXE=0), writing transmission data to TDR sets SSR:TDRE=0. Then
serial chip select pin (SCS) will become active, transmission will be started after the setup time is passed
for the serial chip select pin. The start of the transmission resulted in outputting the transmission data in
synchronization with a falling edge of the serial clock (SCK) output.
(2) Outputting the transmission data in the first bit sets SSR:TDRE=1, and the transmission interrupt is
enabled (SCR:TIE=1), a transmission interrupt request will be generated. At this time, the transmission
data in the second byte can be written.
(3) After the number of data set in the TBYTE is completed for transmission, transmission operation will be
terminated.
(4) After hold time for the serial chip select pin is passed after the transmission operation, the serial chip
select pin (SCS) will become inactive. However, if serial chip select active level (SCSCR:SCAM="1") is
held at this time, the serial chip select pin (SCS) will remain active.
Reception operation
(1) With serial data output disabled (SMR:SOE=0), transmission operation enabled (SCR:TXE=1), and
reception operation enabled (SCR:RXE=1), writing dummy data to TDR makes the serial chip select pin
(SCS) active and reception operation will be started after the setup time is passed for the serial chip select
pin. The start of the reception resulted in sampling the reception data at a rising edge of the serial clock
output (SCK).
(2) Receiving the last bit sets SSR:RDRF=1 and when the reception interrupt is enabled (SCR:RIE=1), a
reception interrupt request will be generated. At this time, the receive data (RDR) can be read.
(3) Reading the received data (RDR) clears SSR:RDRF to "0".
(4) After the number of data set in the TBYTE is completed for reception, reception operation will be
terminated.
(5) After hold time for the serial chip select pin is passed after the reception operation, the serial chip select
pin (SCS) will become inactive. However, if serial chip select active level (SCSCR:SCAM="1") is held at
this time, the serial chip select pin (SCS) will remain active.
Notes:
⋅
When you make reception operation only, make sure to write a dummy data to the TDR in order to
output the serial clock (SCK).
⋅
When transmission/reception FIFO is enabled, setting desired number of frame to be transferred to the
FBYTE register will make serial clock (SCK) output for the setup number of frames.
Transmission/Reception operation
(1) To perform transmission and reception at the same time, enable serial data output (SMR:SOE=1) and
enable transmission/reception operation (SCR:TXE, RXE=1).
(2) When transmission data is written in TDR, SSR:TDRE=0 is set, and then serial chip select pin (SCS) will
become active and transmission/reception will be started after the setup time has passed for the serial chip
select pin. When transmission/reception is started, the transmission data is output in synchronization with
the falling edge of serial clock (SCK) output. When transmission data of the first bit is output,
SSR:TDRE=1 is set, and when transmission interrupt is enabled (SCR:TIE=1), a transmission interrupt
request is output. At this time, the transmission data of the second byte can be written.
MB91520 Series
MN705-00010-1v0-E
1509