Fujitsu FR81S 사용자 설명서
CHAPTER 51: TIMING PROTECTION UNIT
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
22
5.1. TPU Control Register Access Protection
The section explains the TPU control register access protection.
The TPU register is permitted to access only in the privileged mode because all TPU registers are the
system registers. The illegal instruction exception (data access error) is generated if accessing it in the user
mode.
TPU has the function not only that the access protection as the system register, but also it has the function
that the register access protection by the Lock code to prevent the TPU control register is written by
accident due to the malfunction,
The target registers of the access protection are the following two registers.
TPU configuration register ( TPUCFG )
TPU timer control register 10 to 17 (TPUTCN10 to 17)
To make the TPU control register access protection effective, write the values other than a present set value
of UNLOCK[31:0] in the TPU unlock register (TPUUNLOCK). When the access protection function
becomes effective, the LST bit of the TPU lock status register is set and it is shown to be lock state.
When writing it in the control register of the protection target , the value set last time is written in
UNLOCK[31:0]. It becomes TPULST.LST=0 and the unlock state when the lock is released.
After generating reset, the register access protection function is invalid state (TPULST.LST=0).
When the TPU control register access protection function is effective(TPULST.LST=1), and when the
values other than UNLOCK[31:0] are written in TPU unlock register (TPUUNLOCK)the error reply is
returned to AHB and the illegal data access exception is generated in CPU as an illegal access.
Then, the violation factor is set in the TPU access violation detection register (TPUVST.IULST=1) .
When the TPU control register access protection function is effective(TPULST.LST=1), and when the
writing request is in TPU control register (TPUCFG) and TPU timer control register (TPUTCFG1n), the
illegal data access exception is generated in CPU as an illegal access.
Then, the violation factor is set in the TPU access violation detection register (TPUVST.IULST=1) .
Moreover, it is judged that the access by the instruction fetch is a malfunction and generates the illegal
instruction exception. Then, it becomes TPUVST.AVST=1.
MB91520 Series
MN705-00010-1v0-E
2189