Premier Mounts CDM-600 사용자 설명서
CDM-600 Satellite Modem
Revision 7
Summary of Specifications MN/CDM600.IOM
15–6
LDPC CODEC BER
Rate 2/3 8-PSK
Rate 3/4 8-PSK
(With two adjacent
carriers, each 7 dB
higher than the desired
carrier)
Rate 2/3 8-PSK
Rate 3/4 8-PSK
(With two adjacent
carriers, each 7 dB
higher than the desired
carrier)
For:
BER=10
-5
BER=10
-9
8-PSK Rate 2/3 LDPC
Guaranteed Eb/No:
(typical value in
parentheses)
-
5.7 dB (5.2 dB)
8-PSK Rate 3/4 LDPC
Guaranteed Eb/No:
(typical value in
parentheses)
5.7 dB (5.3 dB)
6.0 dB (5.6 dB)
LDPC CODEC BER
Rate 2/3 8-QAM
Rate 3/4 8-QAM
(With two adjacent
carriers, each 7 dB
higher than the desired
carrier)
Rate 2/3 8-QAM
Rate 3/4 8-QAM
(With two adjacent
carriers, each 7 dB
higher than the desired
carrier)
For:
BER=10
-5
BER=10
-9
8-QAM Rate 2/3 LDPC
Guaranteed Eb/No:
(typical value in
parentheses)
4.6 dB (4.2 dB)
5.0 dB (4.6 dB)
8-QAM Rate 3/4 LDPC
Guaranteed Eb/No:
(typical value in
parentheses)
5.2 dB (4.7 dB)
5.7 dB (5.3 dB)
LDPC CODEC BER
Rate 3/4 16-QAM
(With two adjacent
carriers, each 7 dB
higher than the desired
carrier)
Rate 3/4 16-QAM
(With two adjacent
carriers, each 7 dB
higher than the desired
carrier)
For:
BER=10
-5
BER=10
-5
16-QAM Rate 3/4 LDPC
Guaranteed Eb/No:
(typical value in
parentheses)
6.8 dB (6.2 dB)
7.1 dB (6.8 dB)
Plesiochronous/
Doppler Buffer
Doppler Buffer
Selectable size of 64 to 262,144 bits, in 16-bit steps (with added limitations for G.704 frame
boundaries)
Size selection is displayed in bytes and milliseconds
Supports asymmetric operation - when buffer is clocked from Tx clock, Rx and Tx rates do not need to
be identical
boundaries)
Size selection is displayed in bytes and milliseconds
Supports asymmetric operation - when buffer is clocked from Tx clock, Rx and Tx rates do not need to
be identical
Monitor Functions
Eb/No estimate, 2 to 16 dB (
± 0.25 dB accuracy)
Corrected Bit Error Rate, 1E-3 to 1E-10
Frequency offset,
Frequency offset,
± 32 kHz range, 100 Hz resolution
Buffer fill state, in percent
Receive signal level (-20 to -60 dBm, accuracy is
Receive signal level (-20 to -60 dBm, accuracy is
± 2.5 dB)
15.3
Data Interfaces
Primary Data
(3 selectable modes)
(3 selectable modes)
RS-422/EIA-530 DCE (Rates up to 10 Mbps)
(also supports X.21 DCE & DTE and 8k ESC orderwire for IDR)
V.35 DCE (Rates up to 10 Mbps)
Synchronous EIA-232 (Rates up to 300 kbps)
LVDS serial (Rates up to 20 Mbps)
HSSI - Requires optional CIC-20 Converter (Rates up to 20 Mbps)
(also supports X.21 DCE & DTE and 8k ESC orderwire for IDR)
V.35 DCE (Rates up to 10 Mbps)
Synchronous EIA-232 (Rates up to 300 kbps)
LVDS serial (Rates up to 20 Mbps)
HSSI - Requires optional CIC-20 Converter (Rates up to 20 Mbps)
25-pin D-sub (female)
G.703 (Tx In, Drop Out,
Insert In, Rx Out)
Insert In, Rx Out)
1.544 Mbps T1 (Balanced 100
Ω)
6.312 Mbps T2 (unbalanced 75
Ω or balanced 110 Ω)
2.048 Mbps E1 (unbalanced 75
Ω or balanced 120 Ω)
8.448 Mbps E2 (unbalanced 75
Ω)
Note: All Drop and Insert modes are a FAST option.
15-pin D-sub (female)
or BNC (female)
or BNC (female)
External Reference In
2.4 kHz - 10 MHz, in 1 Hz steps (locks baseband clocks only)
TTL level (unbalanced) or sine wave @ 0dBm nominal
TTL level (unbalanced) or sine wave @ 0dBm nominal
BNC (female)
Overhead Data
RS-422 octet clocks for IDR ESC & IBS
RS-422 IDR 64 kbps ESC data & clock
RS-232 IBS ESC data & clock
RS-422 External Clock input
IDR BWA Inputs
RS-232 High Rate ESC data (FAST, with Firmware V. 1.3.1 or higher)
RS-232 ESC++ data ( with Firmware V. 2.0.1 or higher)
RS-422 IDR 64 kbps ESC data & clock
RS-232 IBS ESC data & clock
RS-422 External Clock input
IDR BWA Inputs
RS-232 High Rate ESC data (FAST, with Firmware V. 1.3.1 or higher)
RS-232 ESC++ data ( with Firmware V. 2.0.1 or higher)
25-pin D-sub (male)