Texas Instruments TMS320C645x DSP 사용자 설명서
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5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)
EMAC Port Registers
The MAC interrupt mask set register (MACINTMASKSET) is shown in
and described in
.
Figure 47. MAC Interrupt Mask Set Register (MACINTMASKSET)
31
16
Reserved
R-0
15
2
1
0
Reserved
HOST
STAT
MASK
MASK
R-0
R/WS-0
R/WS-0
LEGEND: R = Read only; R/W = Read/Write; R/WS = Read/Write 1 to set; -n = value after reset
Table 47. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1
HOSTMASK
Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0
STATMASK
Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
102
SPRU975B – August 2006