Texas Instruments TMS320C645x DSP 사용자 설명서
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2.9.1.4
Collision-Based Receive Buffer Flow Control
2.9.1.5
IEEE 802.3X Based Receive Buffer Flow Control
EMAC Functional Architecture
Collision-based receive buffer flow control provides a means of preventing frame reception when the
EMAC is operating in half-duplex mode (FULLDUPLEX bit is cleared in MACCONTROL register). When
receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam
sequence transmitted is the twelve byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3 in
hexadecimal. The jam sequence begins approximately when the source address starts to be received.
Note that these forced collisions are not limited to a maximum of 16 consecutive collisions, and are
independent of the normal back-off algorithm.
EMAC is operating in half-duplex mode (FULLDUPLEX bit is cleared in MACCONTROL register). When
receive flow control is enabled and triggered, the EMAC generates collisions for received frames. The jam
sequence transmitted is the twelve byte sequence C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3.C3 in
hexadecimal. The jam sequence begins approximately when the source address starts to be received.
Note that these forced collisions are not limited to a maximum of 16 consecutive collisions, and are
independent of the normal back-off algorithm.
Receive flow control does not depend on the value of the incoming frame destination address. A collision
is generated for any incoming packet, regardless of the destination address, if any EMAC enabled
channel’s free buffer register value is less than or equal to the channel’s flow threshold value.
is generated for any incoming packet, regardless of the destination address, if any EMAC enabled
channel’s free buffer register value is less than or equal to the channel’s flow threshold value.
IEEE 802.3x based receive buffer flow control provides a means of preventing frame reception when the
EMAC is operating in full-duplex mode (the FULLDUPLEX bit is set in the MACCONTROL register). When
receive flow control is enabled and triggered, the EMAC transmits a pause frame to request that the
sending station stop transmitting for the period indicated within the transmitted pause frame.
EMAC is operating in full-duplex mode (the FULLDUPLEX bit is set in the MACCONTROL register). When
receive flow control is enabled and triggered, the EMAC transmits a pause frame to request that the
sending station stop transmitting for the period indicated within the transmitted pause frame.
The EMAC transmits a pause frame to the reserved multicast address at the first available opportunity
(immediately if currently idle, or following the completion of the frame currently being transmitted). The
pause frame contains the maximum possible value for the pause time (FFFFh). The EMAC counts the
receive pause frame time (decrements FF00h to 0) and retransmits an outgoing pause frame, if the count
reaches zero. When the flow control request is removed, the EMAC transmits a pause frame with a zero
pause time to cancel the pause request.
(immediately if currently idle, or following the completion of the frame currently being transmitted). The
pause frame contains the maximum possible value for the pause time (FFFFh). The EMAC counts the
receive pause frame time (decrements FF00h to 0) and retransmits an outgoing pause frame, if the count
reaches zero. When the flow control request is removed, the EMAC transmits a pause frame with a zero
pause time to cancel the pause request.
Note that transmitted pause frames are only a request to the other end station to stop transmitting.
Frames that are received during the pause interval are received normally (provided the receive FIFO is not
full).
Frames that are received during the pause interval are received normally (provided the receive FIFO is not
full).
Pause frames are transmitted if enabled and triggered, regardless of whether or not the EMAC is
observing the pause time period from an incoming pause frame.
observing the pause time period from an incoming pause frame.
The EMAC transmits pause frames as described below:
•
The 48-bit reserved multicast destination address 01.80.C2.00.00.01h.
•
The 48-bit source address (set via the MACSRCADDRLO and MACSRCADDRHI registers).
•
The 16-bit length/type field containing the value 88.08h.
•
The 16-bit pause opcode equal to 00.01h.
•
The 16-bit pause time value of FF.FFh. A pause-quantum is 512 bit-times. Pause frames sent to
cancel a pause request have a pause time value of 00.00h.
cancel a pause request have a pause time value of 00.00h.
•
Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames).
•
The 32-bit frame-check sequence (CRC word).
All quantities are hexadecimal and are transmitted most-significant-byte first. The least-significant-bit
(LSB) is transferred first in each byte.
(LSB) is transferred first in each byte.
If the RXBUFFERFLOWEN bit in the MACCONTROL register is cleared while the pause time is nonzero,
then the pause time is cleared and a zero count pause frame is sent.
then the pause time is cleared and a zero count pause frame is sent.
SPRU975B – August 2006
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
47