Texas Instruments TMS320C3x 사용자 설명서
Indirect Addressing
6-5
Addressing Modes
6.4
Indirect Addressing
Indirect addressing specifies the address of an operand in memory through the
contents of an auxiliary register, optional displacements, and index registers as
shown in Example 6–2. Only the 24 LSBs of the auxiliary registers and index
registers are used in indirect addressing. The auxiliary register arithmetic units
(ARAUs) perform the unsigned arithmetic on these lower 24 bits. The upper
eight bits are unmodified.
contents of an auxiliary register, optional displacements, and index registers as
shown in Example 6–2. Only the 24 LSBs of the auxiliary registers and index
registers are used in indirect addressing. The auxiliary register arithmetic units
(ARAUs) perform the unsigned arithmetic on these lower 24 bits. The upper
eight bits are unmodified.
Example 6–2. Auxiliary Register Indirect
An auxiliary register (AR
n) contains the address of the operand to be fetched.
Operation:
operand address = AR
n
Assembler Syntax:
*AR
n
Modification Field:
11000
24
23
Address
0
31
x
x
ARn
31
0
Operand
The flexibility of indirect addressing is possible because the ARAUs on the
’C3x modify auxiliary registers in parallel with operations within the main CPU.
Indirect addressing is specified by a 5-bit field in the instruction word, referred
to as the mod field (shown in Table 6–2). A displacement is either an explicit
unsigned 8-bit integer contained in the instruction word or an implicit displace-
ment of 1. Two index registers, IR0 and IR1, can also be used in indirect
addressing, enabling the use of 24-bit indirect displacement. In some cases,
an addressing scheme using circular or bit-reversed addressing is optional.
Generating addresses in circular addressing is discussed in Section 6.7 on
page 6-21; bit-reversed addressing is discussed in Section 6.8 on page 6-26.
’C3x modify auxiliary registers in parallel with operations within the main CPU.
Indirect addressing is specified by a 5-bit field in the instruction word, referred
to as the mod field (shown in Table 6–2). A displacement is either an explicit
unsigned 8-bit integer contained in the instruction word or an implicit displace-
ment of 1. Two index registers, IR0 and IR1, can also be used in indirect
addressing, enabling the use of 24-bit indirect displacement. In some cases,
an addressing scheme using circular or bit-reversed addressing is optional.
Generating addresses in circular addressing is discussed in Section 6.7 on
page 6-21; bit-reversed addressing is discussed in Section 6.8 on page 6-26.
Table 6–2 lists the various kinds of indirect addressing, along with the value
of the modification (mod) field, assembler syntax, operation, and function for
each. The succeeding 17 examples show the operation for each kind of indi-
rect addressing. Figure 6–3 on page 6-20 shows the format in the instruction
encoding.
of the modification (mod) field, assembler syntax, operation, and function for
each. The succeeding 17 examples show the operation for each kind of indi-
rect addressing. Figure 6–3 on page 6-20 shows the format in the instruction
encoding.