Texas Instruments TMS320C3x 사용자 설명서

Interlocked Operations

 

7-14

The LDFI and LDII instructions perform the following actions:

1) Simultaneously set XF0 to 0 and begin a read cycle. The timing of XF0 is

similar to that of the address bus during a read cycle.

2) Execute an LDF or LDI instruction and extend the read cycle until XF1

is set to 0 and a ready (RDY

int

 or XRDY

int

) is signaled. The read cycle

completes one H1/H3 cycle after the XF1 signal is detected.

3) Leave XF0 set to 0 and end the read cycle.

The timing diagrams for LDFI and LDII shown on the data sheets depict a 0
wait state read cycle. Since the read cycle is extended for one H1/H3 cycle
after XF1 signal is detected, the data sheets show the XF1 signal sampled
one H1/H3 cycle before setting the XF0 signal low.

For the sequence of steps described here, the read cycle finishes one H1/H3
cycle after the XF1 signal is detected.

The read/write operation is identical to any other read/write cycle except for
the special use of XF0 and XF1. The 

src operand for LDFI and LDII is always

a direct or indirect memory address. XF0 is set to 0 only if the 

src is located

off chip; that is, STRB, STRB0, STRB1, MSTRB, or IOSTRB is active, or the
src is one of the on-chip peripherals. If on-chip memory is accessed, then XF0
is not asserted, and the operation executes as an LDF or LDI from internal
memory.

The STFI and STII instructions perform the following operations:

1) Simultaneously set XF0 to 1 and begin a write cycle. The timing of XF0 is

similar to that of the address bus during a write cycle.

2) Execute an STF or STI instruction and extend the write cycle until a ready

(RDY

int

 or XRDY

int

) is signaled.

As in the case for LDFI and LDII, the 

dst of STFI and STII affects XF0. If dst

is located off chip (STRB, STRB0, STRB1, MSTRB, or IOSTRB is active) or
the 

dst is one of the on-chip peripherals, XF0 is set to 1. If on-chip memory is

accessed, then XF0 is not asserted and the operation executes as an STF or
STI to internal memory.

The SIGI instruction functions as follows:

1) Sets XF0 to 0
2) Idles until one H1/H3 cycle after XF1 is set to 0
3) Sets XF0 to 1 and ends the operation